Programming SPI-Flash with CycloneV-FPGA

[gotwer]

Hello everyone,

I would like to programme an SPI flash via JTAG with a CycloneV FPGA.
The FPGA is configured in PS mode.

The data to be written is a binary file with data no design.
What do I have to do to use the SFL routine in Quartus Prime.
Can someone help me with an example?

Thank you very much

[FvM]

Hi,
according to Intel knowledge base, it's not possible to use SFL with non-AS configuration mode. https://www.intel.com/content/www/us/en/support/programmable/articles/000074632.html
I understand this so that the SFL IP connection to AS interface atom doesn't work with other configuration mode. The question is if the problem can be bypassed modifying by editing the IP code.

[FvM]

Look at quartus\libraries\megafunctions\altserial_flash_loader.vhd. It instantiates cyclonev_asmiblock to get access to the AS flash port. This internal component is only available in AS configuration mode.

To use SFL for data flash under PS mode, you need to outcomment asmi_block and export flash interface to alternative  top level pins.

[Fakhrul]

Hi gotwer,

Following FvM's suggestion above, do you have any updates for us?

Regards,

Fakhrul