Cyclone V part number 5CEBA7F27C8N

[ShivaKi]

Hello,

In the Cyclone V part 5CEBA7F27C8N, please provide below inputs

1. The slew rate given in datasheet is mentioned as HIGH or LOW, could you provide the slew rate value for HIGH and LOW.

2. During power-up or before and during configuration if 3.3V +/- 10% signal is applied to User I/O pins of Cyclone V, will it make Cyclone V misbehave or configuration not happening successfully?

3. In Device Handbook, the timing diagram(figure 7-2) says user IO Hi-Z but flow chart 7-1 says weak pull-up? Please confirm which is correct. And also, provide weak pullup resistor value during configuration and power up?

[AqidAyman_Intel]

Hello,

For Q1, is this for output pin? Can you point to us the link that mentioned High and Low slew rate in the datasheet?

[ShivaKi]

Hello,

Q1 is regarding Output pin. For example, the  FPGA pin configured as output pin and its slew rate can be programmed as Slow(0) and Fast(1). 

Reference Document: CycloneV Device Handbook Volume 1: Device Interfaces and Integration, Table 5-24: Summary of Supported Cyclone V Programmable IOE Features and Settings 

[AqidAyman_Intel]

For Q2, Cyclone V device support hot-socketing feature where signals can be driving I/O pins before or during power up and power down without damaging the device. Refer https://www.intel.com/content/www/us/en/docs/programmable/683375/current/hot-socketing-feature.html. However, please be aware on the +-10% of 3.3V as it might exceed maximum value from the datasheet. Please also noted on the Power-On-Reset (POR) monitoring certain power supplies where it keeps the Cyclone® V device in the reset state until the power supply outputs are within the recommended operating range.

For Q3, both is correct as the I/O pins are tied to weak pull up that is why the pin is experiencing high impedance (High Z).

[ShivaKi]

Hello,

Related to Q3: During powerup and configuration, if user IO pins are connected to external supply voltages(coming from signals connected from other sources), Will it cause issue with Cyclone V device or for Configuring Cyclone V device.

Please confirm

[AqidAyman_Intel]

Hello,

Thank you for your clarification on Q1. We do not specify the value for Fast or Slow slew rate because it largely depends on the load that the signal is driving to. However, you could use the IBIS model to do signal integrity simulation to verify the behavior of different slew rate to your setup. This will help you to select the optimal slew rate for your setup. Generally, faster slew rate you can have higher fmax, but SI might degrade due to reflection. Slower slew rate you get lesser fmax but less reflection issue.

Regards,

Aqid

[AqidAyman_Intel]

Hi,

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