Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20689 Discussions

MAX10 10M04 Flash Problems

Martin57
Beginner
773 Views

We are using the 10M04SCE144C8G. After about 1 year in the field, we now have already 2 returns from our customer -- "FPGA not booting". When reading out the actual flash-content, we could see 1 sector erased (0xff). On both devices it is the same sector!

Any ideas?

Regards Martin

0 Kudos
10 Replies
JohnT_Intel
Employee
764 Views

Hi,


May I know if you implemented On Chip Flash IP into the design or anyone accidentally performed erase through JTAG?


0 Kudos
Martin57
Beginner
753 Views

Hi John,

JTAG is not connected under this condition, and yes, the IP-Core is implemented. An accidential access from User-Level seems highly unlikely, and on System-Level there is only code for "bulk-erase". In my case, there are only a few Bytes (one sector?), erased to 0xff.

Regards Martin 

 

0 Kudos
Martin57
Beginner
743 Views

Hi John,

in case, it would be helpfull for you, I attached the original and the readout-file

0 Kudos
JohnT_Intel
Employee
731 Views

Hi,


Could you confirm after you write into the flash, that particular mismatch is being written correctly? The reason is that there is no way that user is able to write a 0xFF into location except if erased happen.


I suspected that the data is written partially towards the end of the flash.


0 Kudos
Martin57
Beginner
726 Views

Hi John,

YES, I can confirm, the data was written / verified correctly! - This issue arises about 1 year of function in the field. At the moment, we have 2 failures out of 200.

 

0 Kudos
JohnT_Intel
Employee
723 Views

Hi,


The only think I can think of is that the erase has been accidentally performed from the On Chip Flash IP. I observed that the erased location is starting from Address 0x46000. Could you help to check if the CFM is having the write access or anything that can accidentally performed page erase?


0 Kudos
Martin57
Beginner
718 Views

Hi John,

so, 0x46000 matches with a sector/page-boundary?

The CPU has all the time access to the IP Core Control Registers, so, for example during brown-out conditions,  the occurence of a write_access is not absolutely impossible...

But, as far as I understood:

I would need at least 2 accesses to the command_register -- First to enable "sector_write", second the selected page -- very unlikely 

How can I be sure, that this issue MUST BE due to an accidentally  access?

 

 

0 Kudos
JohnT_Intel
Employee
709 Views

Hi,


The reason is that the flash will not be accidentally erase on certain location and there is no way for user to write a ''1' into the flash as only write '0' bit is possible for this flash. Based on my calculation, the address provided should be the starting address of the page.


0 Kudos
Martin57
Beginner
701 Views

Hi John,

thanks for your response!

But, might there be other reasons for this failure?

-- "half programmed" Flash, due to timing/voltage during programming, so it looses one complete page-data?

-- in our design, the pin "config_sel" is strapped to "1", and we are programming "single image"

0 Kudos
JohnT_Intel
Employee
686 Views

Hi,


If there is some issue, I would suspect that you should observed the full flash erase rather than certain location erased.


0 Kudos
Reply