Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Объявления
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Обсуждение

Purpose of WIRE buffer in BDF

Altera_Forum
Почетный участник II
1 346Просмотр.

What is the purpose of the "WIRE" buffer in BDF schematics ? 

The reason for asking is related to the Verilog "WIRE", which I understand to be analogous to a VHDL "SIGNAL" (I don't know Verilog). 

A previous thread explained "WIRE" to be ~ "a way to connect things", but in BDF you have the graphical wiring tool. 

So, if coding BDF, when and why sould the "WIRE" buffer be used ? 

In the schematics below, is there a difference between "circuit1" and "circuit2" ? 

 

in1 ----|>----- out1 // circuit 1 - "|>" is a WIRE-buffer 

 

in2 ------------ out2 // circuit 2
0 баллов
3 Ответы
Altera_Forum
Почетный участник II
660Просмотр.

Hi, 

 

 

--- Quote Start ---  

In the schematics below, is there a difference between "circuit1" and "circuit2" ? 

 

in1 ----|>----- out1 // circuit 1 - "|>" is a WIRE-buffer 

 

in2 ------------ out2 // circuit 2 

--- Quote End ---  

 

 

There will be no difference.  

 

 

--- Quote Start ---  

So, if coding BDF, when and why sould the "WIRE" buffer be used ? 

--- Quote End ---  

 

 

For example when changing names.
Altera_Forum
Почетный участник II
660Просмотр.

Both serve the same purpose. But the Wire buffer has a buffer in between. This can be used to insert delays in the line and also to improve the drive strength / fan-out of such signals.

Altera_Forum
Почетный участник II
660Просмотр.

 

--- Quote Start ---  

Both serve the same purpose. But the Wire buffer has a buffer in between. This can be used to insert delays in the line and also to improve the drive strength / fan-out of such signals. 

--- Quote End ---  

 

 

It wouldnt do this by default - duplicate logic is usually optimised away, unless specified max fan outs are reached, or attributes/assignments are made. Maybe in old compilers in old technologies would this have been possible without using attributes or assignments. 

The wire primitive in BDF doesnt have much more use than a signal re-naming block.
Ответить