QSys output code won't compile - Arria II GX with simple socket server example

[Altera_Forum]

I haven't found any examples of the simple socket server specifically for the Arria II GX, so I'm taking the example for other boards (Stratix, etc.) and using a tse block for the MAC in my QSys system. When I connect the tse block's transmit and receive source and sink to SGDMA blocks the code generated by QSys doesn't compile in Quartus. QSys generation doesn't report any errors, but here are the error messages from Quartus: 

 Error (10528): VHDL error at NIOSTest.vhd(8125): value "0" is outside the target constraint range (1 to 2147483647) Error (10528): VHDL error at NIOSTest.vhd(8126): value "0" is outside the target constraint range (1 to 2147483647) Error (10528): VHDL error at NIOSTest.vhd(8132): value "0" is outside the target constraint range (1 to 2147483647)  The code fragment that generates the errors has '0' set for ChannelWidth in 3 places:  avalon_st_adapter : component NIOSTest_avalon_st_adapter  generic map (  inBitsPerSymbol => 8,  inUsePackets => 1,  inDataWidth => 32,  inChannelWidth => 0,  inErrorWidth => 0,  inUseEmptyPort => 1,  inUseValid => 1,  inUseReady => 1,  inReadyLatency => 0,  outDataWidth => 32,  outChannelWidth => 0,  outErrorWidth => 1,  outUseEmptyPort => 1,  outUseValid => 1,  outUseReady => 1,  outReadyLatency => 0  )  port map (  Does anyone know why these widths are being set to zero, or if there's a work-around for this? To help isolate this problem, if I don't connect transmit/receive source and sink these errors don't occur. All files generated by QSys have been added to the Quartus project so I don't think there's an issue there. (I checked the dev kit software for the Arria II GX board, and nothing there references the PHY, except for pin designations. There is a link somewhere in the Altera world to a tse/JTAG example for this board, but that link is broken.)  Thanks, Tom

[Altera_Forum]

Can you try to regenerate the TSE core from scratch for Arria II GX by referring to the parameter in the example?

[Altera_Forum]

Thanks for the quick response, but I'm not sure how to implement your suggestion. Is this something I can do from Qsys (where eth_tse is included in the project) or do I need to do it with tcl? Qsys tells me all of my cores are up to date. Info on the web talks about upgrading/regenerating cores under Quartus, but I'm not generating eth_tse under Quartus.

[Altera_Forum]

You can try to locate the TSE MAC IP core in the Qsys library to see if can find it?

[Altera_Forum]

Upgraded to Quartus 13.1 from 13.0 and the problem went away. Glad it's working, but not feeling warm fuzzies about the software tools.