Qsys can't find hps pin info

Altera_Forum · ‎08-30-2014

I have a new Terasic DE1-Soc Rev D. which has a 5CSEMA5F31C6N

I am unable to get qsys to find the pin info for the hps component. Thus, it refuses to generate hdl.

The error in the tool is

Error: soc_system.hps_0: The pin information for the Hard Processor System could not be determined. Please check whether your edition of Quartus II supports the selected device.

I'm new to the quartus tool chain and it feels like perhaps I've overlooked some basic setup step. Naively, I would have expected some sort of board definition package similar to the device .qdz that also needs to be additionally installed after the device.qdz and would provide canonical pin names based on actual board trace peripheral connections, detailed sdram timing & arch, etc and other board specific info. But, I can't find any such thing or any mention of something like that.

I am able to build and install the basic blinky-light verilog samples that came with the board. And, I've verified that I can modify them and my changes show up. So, the fundamental tool chain is working.

SW versions:

windows 8

Quartus II web edition 64-bit (14.0.0.200) same problem with or without 14.0.1.205 patch

ModelSim 14.0.0.200

CycloneV- 14.0.0.200.qdz

The Web vs. subcription edition detailed comparison here: http://www.altera.com/literature/po/ss_quartussevswe.pdf

Says that the web edition supports qsys on all cyclone V socs.

I have tried a couple of different things with qsys.

I am Following workshop lab here:

http://www.rocketboards.org/foswiki/documentation/arrowsockitevaluationboard#workshop_labs

except that I'm generating the qsys project from scratch because of minor differences between the board peripherals and slightly different c5 model.

I've also tried directly loading Terasic's similar but much less detailed walkthrough on their system CD in demonstrations\SOC_FPGA\my_first_hps-fpga_base \<sample project> and UserManual\My_First_HPS-Fpga.pdf since it contains a pre-existing project for the right board and periperal.

I have the same qsys error with either the project I create from scratch or when I open the full Terasic sample that came with the board CD download.

Web search with multiple search engines turns up no mention of this specific error message

Does anyone have any idea what I'm missing? What file(s) and directory is supposed to contain the pin information?

thanks

Altera_Forum · ‎09-04-2014

Hmmm that's odd. To eliminate Quartus from the mix try compiling a design like this as the top level (i.e. no HPS):


module top (
    a,
    b);
  input a;
  output wire b;
  assign b = ~a;

This will determine if the web version can compile any design that targets an SoC device. If that works then I'm guessing there is a Qsys bug or perhaps the device selected in Qsys doesn't match the device settings for your Quartus project.

Altera_Forum · ‎09-05-2014

I am able to build and run plain Verilog from Quartus on the device without any problem. the issue i'm having is that qsys won't generate hdl because it says it has no pin info. this seems to be strictly a qsys issue. i'm using the same device in quartus and qsys.

thanks

Altera_Forum · ‎09-09-2014

If you haven't already done so I would file a support ticket for Altera to look into this: http://www.altera.com/mysupport

I just tried to target that same device with the full version and was able to generate the HPS block in Qsys. I'll ask around to see if that web edition document is up to date.