Qsys poor fmax peformance

[Altera_Forum]

Hi, 

 I just want to know if somebody has experienced the same issue. I took an old SOPC Bulider design, compiled with Q8.1 for a EP3C25F256C8 device and used Q11 to convert it to Qsys. As SOPC buildersystem compiled with Q8.1 the design can run at 75MHz without any timinig errors. When I do not change anything after the conversion to Qsys the Fmax decreases to 64 MHz (no pipeline, fully combinational). By adding 1,2 or 3 pipeline stages the fmax increases to 73-74 Mhz (without changing optimization settings). Only with 4 pipeline stages 75 Mhz can be achieved. This increases the resource usage from approx. 14000 LEs (Q8.1 SOPC Bulider) to 21000 LEs (Qsys). Addtionally this adds a big latency to the accesses. According to wth WP "Applying the Benefits of Network on a Chip Architecture to FPGA System Design" the fmax performance of a Qsys design with no pipeline stages should be as fast or even faster than a traditional system. Just marketing ?? Maybe there is another Qsys setting which can increase fmax performance, which a did not find. Any ideas ?  Regards, HJS

[Altera_Forum]

Hello, 

 I compiled a small system to test if the Fmax was greater in Qsys. I could achieve greater Fmax in Qsys than in SOPC. [178.5 Vs 157.7[sopc]] and this was without pipe-lining.  Thanks, Aditya.

[Altera_Forum]

Do you have a lot of fan in/out in your system? (i.e. a master connected to a lot of slaves or a slave connected to a lot of masters). If so you might want to change your topology a bit using bridges (and hierarchy). 

 Also are you constraining your design? If not then I wouldn't put too much faith in Fmax numbers even if it appears that the system works. I would look at the critical paths using Timequest to see where the longest paths are so that you know where to focus your efforts.

[Altera_Forum]

My system does not have lot of fan in/out. It has only one clock. I had a constraint file for different operation frequency. How do I look at the critical Paths in Time-quest ?. I am in the process of developing a moderately big system. I will keep you posted on the Fmax results.

[Altera_Forum]

Another thing that could explain this is if you use large on-chip memories it might be hindering the placement if the memory is getting spread all over the place. 

 Normally when I perform timing analysis I normally start by double clicking the "Report top failing paths" macro. Often when you have some paths that fail by a large margin it can have a negative impact on many other paths in your design so that's why I start with the biggies first.  Once the paths are listed out I find the one with the most negative slack (it's in red) and right click it and select report timing and use the default settings to report the timing. It'll show you the clock and data paths so I normally drill down to the data path and look at all the incremental delays and try to figure what portion of my design would contribute to it.  All this said.... Also run "Report Unconstrained Paths" diagnostic since it'll tell you if you lack constraints. If you lack I/O constraints then that'll could have a huge impact on your Fmax.

[Altera_Forum]

I have the unconstrained Path in "red". So I think this is increasing my Fmax

[Altera_Forum]

@BadOmen : The system is a very common system with 10 masters and approx. 10 slaves. The resource usage in the EP3C25 is about 62% of LE's and 97% of M9K. As I already mentioned, this is an old SOPC Builder system, which is converted to Qsys. I took the same timing constraints for the Qsys design. The design is properly constraint. With SOPC builder 75 Mhz is not a problem, with Qsys and no pipeline stages Fmax is about 64 MHz. This is only 85% of the fmax performance of the SOPC Bullder design. The top failing path is a NIOS path. It's from IEM:inst|IEM_cpu:cpu|d_read to IEM:inst|altera_merlin_master_translator:cpu_data_master_translator|address_register[24] 

with a total delay of 15.566 ns.

[Altera_Forum]

Connecting the CPU master to a pipeline bridge and then connecting the bridge to the slaves might help. SOPC Builder and Qsys use different interconnect structures so there will be some system architectures that will achieve a higher Fmax in SOPC Builder but in general Qsys will result in faster systems. With 97% memory utilization that would be the first spot I would look for potential optimizations since that is a fairly heavy utilization of the FPGA RAM blocks which will hinder the fitter. Does your SOPC Builder design also result in 97% memory utilization?