Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

Qsys usage for dynamic reconfiguration in StratixV

Altera_Forum
Honored Contributor II
1,059 Views

Hi all,  

 

I need to implement a transceiver configuration in Stratix V where i need to switch between different data rates.  

Before I was working with a Cyclone IV where the Megafunctions for making transceiver implementation were called altgx and altgx_reconfig.  

Now in Stratix V they are called different (PHY fucntions).  

 

I am trying to implement the example of dynamic reconfiguration shown in the document an664 but I don't understand why the use Qsys tool for implementing this Avalon Master-slaver.  

Is is really necessary to create Avalon functions for running a transceiver implementation?  

Or the design can work creating just the Low Latency PHY interface (transceiver interface), the Reconfiguration controller interface and the .MIF files? 

 

Thanks in advance
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
360 Views

What I understood in document an664 is This Avalon-Master slaver is needed in order to connect the reconfiguration controller and the protocol (created with megawizard) to the master in qsys, because the master is the main communication channel between the System Console tool and the slaves in the design.

0 Kudos
Altera_Forum
Honored Contributor II
360 Views

By the way, if you are trying an664 example, I think there is a problem with the external slave interface and that mistake doesn't allowed you to load the design to the board. You should create your own external slave in qsys.

0 Kudos
Reply