Quartus 25.1.1 Pro Fitter Error with Agilex3

[SteffenP]

Hi,

I have an issue trying to compile Verilog project for a Agilex 3 (A3CZ135BB18AE7S) based development board.

The error I'm getting is :

Error (23098): One or more blocks are configured incorrectly and will not have the desired functionality. --BCM instance name: hvio_1_1
Error (12274): A critical error occurred while the periphery placement was committed to the atom netlist. The atom netlist is now invalid and the Fitter must be restarted.
Info (20273): Intermediate fitter snapshots will not be committed because ENABLE_INTERMEDIATE_SNAPSHOTS QSF assignment is disabled during compilation.
Info (20274): Successfully committed planned database.
Error: ERROR: An error occurred during automatic periphery placement

Error: Quartus Prime Fitter was unsuccessful. 3 errors, 2 warnings
   Error: Peak virtual memory: 5771 megabytes
   Error: Processing ended: Tue Sep 23 16:35:45 2025
   Error: Elapsed time: 00:00:26
   Error: System process ID: 763717

I can't find any more information on what is wrong with the code, is there a way for the tool to me more verbose ?

Any helps or hits would be highly appreciated.

Cheers,

Steffen

[SteffenP]

I'm attaching a QAR file.

The issue seems to be related to the "tennm_ph2_ddio_in" instances (or if I use the "GPIO" IP and configure it as DDIO input mode).

Cheers,

Steffen

[ShengN_Intel]

Hi,

May I know using gpio ip also got error?

Could you provide design using gpio ip?

Thanks,

Regards,

Sheng

[SteffenP]

Hi,

Yes, the same error happens if I use the GPIO IP.

I'm attaching an archive with that change, including log files.

Cheers,

Steffen

[ShengN_Intel]

Hi,

If comment the tennm_ph2_ddio_out then the error will disappear. Could you replace tennm_ph2_ddio_out with gpio ip instead of direct using the tennm_ph2_ddio_out to prevent configuration error?

Thanks,

Regards,

Sheng

[SteffenP]

Hi Sheng,

This is what I did in my last reply where I uploaded the Quartus Archive.

Using the GPIO IP does *not* solve the issue.

Cheers,

Steffen

[ShengN_Intel]

Hi Steffen,

In the last design sent, you still use the tennm_ph2_ddio_out and two gpio ip.

If remove the tennm_ph2_ddio_out and keep the gpio ip, there's no more error.

There's problem on configuring the tennm_ph2_ddio_out which causes the issue. I suggest replace tennm_ph2_ddio_out with gpio ip to prevent configuration error.

Thanks,

Regards,

Sheng

[SteffenP]

Hi Sheng,

Ok, sorry I misread your reply. However, I did what you asked now, generated two new GPIO IPs rgmii_out1 and rgmii_out4, and use them instead of the manual instantiations of tennm_ph2_ddio_out.

However I still get the same error.

I have attached the new archive to this case.

Cheers,

Steffen

[SteffenP]

Hi,

I think I've figured it out.

The issue is with the ibuf. If the output of the ibuf somehow gets optimized away, we get this warning. For example I've reduced my example down to a single bit of ibuf and obuf (the CTL part of my original code).

If I do it like this :

   wire               ethphy_sink_valid; // From CDC
   wire [1:0]         ethphy_tx_ctl; // To IO

   assign ethphy_tx_ctl = {2{ethphy_sink_valid}};

   wire               ethphy_source_valid; // To CDC
   wire [1:0]         ethphy_rx_ctl; // From IO

   assign ethphy_source_valid = &ethphy_rx_ctl;

   ipm_cdc_2clks_sync u_ctl_sync
     (.src_clk (eth_rx_clk),
      .src_sig (ethphy_source_valid),
      .dst_clk (eth_tx_clk),
      .dst_sig (ethphy_sink_valid)
      );

it works fine, no error.

However, if I do it like this :

   wire               ethphy_sink_valid; // From CDC
   wire [1:0]         ethphy_tx_ctl; // To IO

   assign ethphy_tx_ctl = {2{ethphy_sink_valid}};

   wire               ethphy_source_valid; // To CDC
   wire [1:0]         ethphy_rx_ctl; // From IO

   assign ethphy_source_valid = ethphy_rx_ctl[1];

   ipm_cdc_2clks_sync u_ctl_sync
     (.src_clk (eth_rx_clk),
      .src_sig (ethphy_source_valid),
      .dst_clk (eth_tx_clk),
      .dst_sig (ethphy_sink_valid)
      );

It fails with this error.

The difference between the two is that in the second case only one of the two output bits from the DDRIO register is used in the CDC transfer (bit[1]), so the other gets optimized away by the compiler. And then the fitter throws this error, which could have been a bit more clear to be honest It does not help even if I use a "keep" attribute on the net.

Even adding a register stage to register both bits doesn't work, because the register for the unused net ultimately gets optimized away.

This happens regardless of using the GPIO IP or the atom primitives directly.

Now I have  a workaround for my specific case at least, but it would be nice if the tool either gave a more clear error on what went wrong, or actually managed to deal with it anyway (either by adding it's own set of register preservation or removing the unused instance).

Cheers,

Steffen

Cheers,

Steffen

[SteffenP]

Hi,

To clarify, the workaround is to add a register with a "noprune" attribute that registers the unused bit of the ddrio ibuf to ensure it doesn't get optimized away :

   wire               ethphy_source_valid; // To CDC
   wire [1:0]         ethphy_rx_ctl; // From IO
   (* noprune *)
   reg                ethphy_rx_ctl0_reg;

   always @(posedge eth_rx_clk) ethphy_rx_ctl0_reg <= ethphy_rx_ctl[0];
   assign ethphy_source_valid = ethphy_rx_ctl[1];

Cheers,
Steffen

[ShengN_Intel]

Hi,

Great to hear that your problem had been resolved and thanks for sharing. Will report to internal team for enhancement on the error message.

Thanks,

Regards,

Sheng