Quartus II DE1 Board clock problems

Altera_Forum · ‎10-05-2010

Hi, we are students that receive the DE1 Altera Board for a university project.

We need to use the 50 MHz clock and divide it to obtain a 2 MHz clock; the project works normally on Quartus II, and there it is:


library ieee;
use ieee.std_logic_1164.all;
entity clk is
port(
--reset  : in std_logic;
ing      : in std_logic;
oclk     : out std_logic
);
end clk;
architecture bev of clk is
signal clk_temp : std_logic :='0';
signal clk_temp_in : std_logic :='0';
begin
oclk<=clk_temp;
clk_temp_in<=ing;
process(clk_temp_in)
 variable cnt : natural := 1;
 begin
 -- conto fino a 25 colpi di clkin per poi dare un colpo di clk a SCLK
 if (clk_temp_in'EVENT and clk_temp_in='1') then
 if ( cnt = 13 ) then clk_temp <= NOT (clk_temp);
 cnt := 1;
 else
 cnt := cnt + 1;
 end if ;
 end if;
 end process;
end bev;

We need to use Simulink, so we use the block "HDL Import" from the DSPBuilder; then we load the VHDL and use the block "Signal Compiler" to generate the project for Quartus; but we have this:

 library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_clock_GNF343OQUJ is
        port(
                aclr : in std_logic;
                aclr_n : in std_logic;
                aclr_out : out std_logic;
                clock : in std_logic;
                clock_out : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_clock_GNF343OQUJ is
Begin
        -- Straight Bypass Clock
        clock_out               <=      clock;
        -- reset logic
        aclr_out                <=      not(aclr_n);
end architecture;

What happened to our code ? We don't understand it. Thank for you help.