Quartus II: Help with bus out and bus in ports

[AVale22]

Hi, sorry for stupid question 😆 , newbie with bus, as you can see I have done 3 chips in vhdl, one without vector, that is simple but bad vhdl code (not optimal) the I have done the other 2 with vector question is how do connect a out bus to a different in port bus, and also the one I have reuse how do i connect different signal to same but different bus ???

see attach image, thx in advance for help 😃

Of course I will want use vectors in VHDL so first chip will be change to vector if bus issues solved 😀

[Vicky1 · Accepted solution]

Hi,

Please check the below solution & take care the rest of the connection in your project like cc[cc[3..1],cc[0]], ccc[ccc[3..1],ccc[0]] & y[y[7..2],y[1],y[0]] etc.

Please let me know if you have any different concern.

If possible you can share the project file *qar file('Project' Menu -> 'Archive Project').

Regards,

Vicky

[AVale22]

Thx, that was what I was think was to solved it :), have apply that and it work fine :)