Quartus II simulation: missing max3000a_ver and output pin stuck at ground

[Niko3]

Hi, I am a beginner with Quartus.

I use Quartus II 13.0sp1 because I want to use a chip from MAX3000A family. Later versions don't support MAX3000A.

To start with a simple design I tested the following circuit (simpleTest.png):

Compilation is ok, but functional simulation with the waveform editor causes two problems.

1) Simulation reports following errors:

• Error: (vsim-19) Failed to access library 'max3000a_ver' at "max3000a_ver"
• Error: (vsim-3033) myTest.vo(76): Instantiation of 'max_mcell' failed. The design unit was not found

•  When I assign a chip from MAX V family, compile and then run functional simulation, there are no such errors, but a second problem comes up.

• 2) I expected a result like this (waveform_need.png):
•  
• 

but I get a result like this (waveform_sim.png):

and the compiler message "Warning (13410): Pin "rsPulse" is stuck at GND"

With another simulation tool (logisim) I get the pulses on rsPulse. In my final circuit they are needed together with further logic to asynchronously clear a counter. These pulses shall rise at the falling edge of CLK. The pulse width may be larger than shown in the diagram above but it shall be somewhat smaller than the low state of CLK.

When functional simulation with a MAX V family is ok then I guess that it would also be ok with MAX3000A. If so then problem 1 no longer exists. If not where can I get 'max3000a_ver' from?

What is wrong with my circuit, problem 2?

If needed the three pictures are attached.

[FvM]

Hello,
you don't consider that Quartus synthesis performs logic minimization. Respectively your asynchronous pulse generation logic is discarded during synthesis. Read Quartus software manual about syn_keep attribute. Applying the attribute to intermediate logic nodes should synthesize the logic as intended. Not sure if the delay is sufficient to generate a stable output pulse, but something of this kind should work.

[Niko3]

Thank you, I will check it.

[SyafieqS]

Let me know if previous suggestion resolve your issue.

[Niko3]

I found another solution: I changed the design to a synchronous clear of the counter which works.

I guess that the advised syn_keep attribute shall be used within a VHDL description of the circuit. But I am testing with the schematic editor and don't know how to get VHDL from it.

If Quartus II can provide such a function it would be very helpful also for other purposes, e.g. for creating a test bench.

[SyafieqS]

What Quartus Edition are you using? Pro, Std/Lite?

FYI, In Std/Lite, I remember there is a feature to convert from schematic to hdl.

You may use that if applicable.

Anyways glad that you resolve the issue.

[Niko3]

I am using Quartus II 13.0sp1.

The problem with

       Error: (vsim-19) Failed to access library 'max3000a_ver' at "max3000a_ver"

still is unresolved.

Where can I get the library max3000a_ver from, for simulation?

[FvM]

Hello,
check below method to keep lcells in schematic design

synthesis result:

Regards,
Frank

[SyafieqS]

Did you see any modelsim ini file generated using the max3000?

Can you try to delete and recompile, and rerun the simulation.

If still persist, seem there is library issue which probably need to resintall.

You can download the device support in here

https://www.intel.com/content/www/us/en/software-kit/711920/intel-quartus-ii-subscription-edition-design-software-version-13-0sp1-for-windows.html

Reinstall the whole device package with Quartus.

Let me know the update

[SyafieqS]

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