Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21345 Discussions

Quartus Issue

Altera_Forum
Honored Contributor II
‎06-02-2011 06:08 AM
1,071 Views

Hi, 

 

I am working on a design which is implemented in Quartus 6.0 Version and it is working well. When I an upgrading this design to Quartus 7.1 Version it's not working.Actually there is H/W and S/W both so what i did in SOPC I added timer (high_res_temer(20 us) and sys_clk_timer(20 ms)) because without timer software was not going to build. These timers were not in Quartus 6.0 project. So can you please tell me what care i shoud take for upgradation in 7.1 version. 

Thanks in advance.
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.