Quartus .SOF Missing

[Altera_Forum]

Hi, 

 I am new user of Cyclone SOC and i have designed a simple project for LEDs, it is working well but when i have tried to program on my FPGA board the .SOF file was missing. I think i could not find it anywhere in my system. Please help me in this regards.  Thank you !  Best regards, Shahbaz

[Altera_Forum]

This file is located in your project folder after you successful compile your design. Especially after the assembler generated the programming file. If errors occure no programming file will be generated.

[Altera_Forum]

There is no error as compilation was successful, the file should be in the project output folder, but there is no such file exists. I am using Quartus II 12.1 it is licensed.

[Altera_Forum]

Under Assignments/Settings/Compilation Process Settings you can define an output file directory for your project. Maybe this is done.

[Altera_Forum]

Furthermore you can look at the Processing Message window for an info like: 

Info: Assembler is generating device programming files

[Altera_Forum]

Well, i have tried this as well but not working.

[Altera_Forum]

Take a look at your Quartus II Tasks Window. 

Are you in the Compilation flow? Can you see the Assembler task under Compile Design?  Is it green?

[Altera_Forum]

--- Quote Start ---  Take a look at your Quartus II Tasks Window. Are you in the Compilation flow? Can you see the Assembler task under Compile Design?  Is it green?  --- Quote End ---     Yes, the following tasks are green  -Fitter (Place and Route) -Assembler (Generate programme files) -TimeQuest Timing Analysis  Moreover, i have design two programs before this one, they were generating .sof but this program is not generating any .sof file.

[Altera_Forum]

Under the Compilation Flow the following task is not green. 

 - EDA Netlist Writer (i have got one warning message) Warning (199027): Can't generate output files. Specify command-line options to generate output files, or update EDA tool settings using GUI or Tcl script.  Could you please help me how to fix this warning ?

[Altera_Forum]

First of all, go to assignments -> settings -> compilation process settings and make sure that "run assembler during compilation" is ticked. 

 You can always manually run the assembler by going processing -> start -> assembler

[Altera_Forum]

--- Quote Start ---  First of all, go to assignments -> settings -> compilation process settings and make sure that "run assembler during compilation" is ticked.  You can always manually run the assembler by going processing -> start -> assembler  --- Quote End ---    Yes , i have checked that option, assembler is working fine but there is one warning under EDA netlist writer Warning (199027): Can't generate output files. Specify command-line options to generate output files, or update EDA tool settings using GUI or Tcl script.  i don't know how to fix this warning.

[Altera_Forum]

Maybe you can post screenshots of your EDA Tool Settings page and the pages below.

[Altera_Forum]

--- Quote Start ---  Maybe you can post screenshots of your EDA Tool Settings page and the pages below.  --- Quote End ---    Here are the attached screenshots of my EDA Tool Settings. please have a look.

[Altera_Forum]

The screenshots looks ok to me. In your case i would try to create the project new and copy the HDL files to the new project.