Quartus Simulation - initializing registers

Altera_Forum · ‎07-04-2009

Hi guys, I'm new to the FPGA scene and could use some help.

I'm designing a project using Verilog HDL. This project derives some computations from previous data stored in registers (reg type).

I'm trying to run a simulation for verification and I want to initialize these registers to a certain value. I've inserted the registers to the .cvwf file and set their values. However when I run the simulation all the registers are zeroed.

How can I manually set those registers' value?

Thank You.

Altera_Forum · ‎07-04-2009

If you're just doing it for simulation, you can:

a) - initialize the register in the declaration like:

reg my_reg = 32'hdeadbeef;

b) - Create an initial block within your code.

reg  my_reg;
initial begin
     my_reg = 32'hdeadbeef;
end

c) - You can also create a macro that you only define for simulation that initializes the code

reg  my_reg;
`ifdef SIMULATION
always @(posedge clk or negedge reset_n)
if(!reset_n) my_reg <= 32'hdeadbeef;
`endif

Jake

Altera_Forum · ‎07-04-2009

Okay I'll try your suggestions.

But just to humor me, is there a way to initialize the registers in the .cvwf file? (Like I would set the clock signal or the reset etc.)

Thank you.