Question Regarding LVDS SERDES Receiver Clock Requirements in Agilex 7 F-Series

[kashi669266]

Hello,

I have a question about the LVDS SERDES in the Agilex 7 F-Series.
The Device Data Sheet mentions the parameter tREFPJ.
Does the rx_inclock of the LVDS SERDES Receiver need to meet this requirement?

I am trying to receive serial data output from Texas Instruments DS90CR481 using the FPGA's LVDS SERDES Receiver.

The SERDES CLOCK is 100MHz with a cycle-to-cycle jitter of 100 ps, which meets the FPGA's tINCCJ requirement, but is likely to not meet the tREFPJ requirement.

[kashi669266]

I apologize for the unclear explanation. Please allow me to explain my concerns more clearly.

I’m assuming a circuit configuration as shown below:

I would like to ask about the following two points:

1. Requirement for tREFPJ
When configuring an LVDS SerDes receiver, is it necessary to meet the tREFPJ specification?
Stratix 10 also includes an LVDS SerDes, but this parameter is not listed in its documentation.

2. Interpretation of tREFPJ
Is it correct to understand tREFPJ as the integrated phase noise power spectral density of the CLK(LVDS) over the frequency range of 10 kHz to 50 MHz?

Thank you for your support.

[WZ2]

Hi there,

1. Your understanding is correct.
2. Do you happen to know the value of tREFPJ for the DS90CR481?
3. Have you observed any noticeable data loss or mis-decoding? Typically, a 100 MHz accompanying clock is not considered a very stringent condition.

Best regards,

WZ

[kashi669266]

Thank you for your response.

I appreciate your explanation. I am not very familiar with jitter theory, so your input was very helpful.

I do not know the value of tREFPJ for the DS90CR481.

We are still in the study phase, and no actual issues have occurred yet. However, I understand now that under the current conditions, there is little cause for concern.

Thank you again for your support.