CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
Success! Subscription added.
Success! Subscription removed.
Sorry, you must verify to complete this action. Please click the verification link in your email. You may re-send via your
profile.
I have tried to use the clock crossing bridge to save the area to improve my design.I think when i use the clock crossing bridge ,the CDC module will be instead.But,after i compile the SOPC i find the CDC is still there.Would you please to tell me what should i if i want to get rid of the CDC module.(I use Quartus7.2SP2). Thanks a lot!
Did you set the correct clocks on the two sides of the clock crossing bridge? The slave side should be the same clock as all masters connected to it. Likewise the master side should be the same clock as all it's slaves.
I set the clocks just like you said.After i compiled the project,there are lots of clock module.Does it mean that the CDC module has been inserted? Or i have misunderstood it?
The problem has sloved,I made a stupid mistake.I have misunderstood the altera's document and what you said.I checked the SOPC,and swap the master and slave's clk ,it happens like what i want it to be.
