Question about the FPGA 10/100 Ethernet (FPGA)

[Altera_Forum]

I want to get some information about how to support the "10/100 Ethernet (FPGA)". 

But I do not searched enough information except below:   10/100 Ethernet (FPGA) The development board supports an RJ-45 10/100 base-T Ethernet using an external Renesas uPD60620 PHY. This PHY supports EtherCAT, Ethernet IRT and DLR features using 3rd party MAC IP. The PHY-to-MAC interface employs MII connection using four data lines at 25 Mbps each for a connection speed of 100 Mbps.   And I have some questions as below:  

1. What is the MAC of the 10/100 Ethernet (FPGA)? 

 . It seems using 3[SUP]rd[/SUP] party MAC IP. But what is it? Is there some manual? . Is the MAC a hard CORE integrated into FPGA so that it cannot be changed or customer can use any MAC IP they want, just need to download to FPGA?  

1. These 2 ports used for EtherCAT(mainly? Only?) or normal TCP/IP? 
2. Is there some app/driver/test that shows how to use it? 

[Altera_Forum]

--- Quote Start ---  I want to get some information about how to support the "10/100 Ethernet (FPGA)". But I do not searched enough information except below:   10/100 Ethernet (FPGA) The development board supports an RJ-45 10/100 base-T Ethernet using an external Renesas uPD60620 PHY. This PHY supports EtherCAT, Ethernet IRT and DLR features using 3rd party MAC IP. The PHY-to-MAC interface employs MII connection using four data lines at 25 Mbps each for a connection speed of 100 Mbps.   And I have some questions as below:  

1. What is the MAC of the 10/100 Ethernet (FPGA)?  

 . It seems using 3[SUP]rd[/SUP] party MAC IP. But what is it? Is there some manual? . Is the MAC a hard CORE integrated into FPGA so that it cannot be changed or customer can use any MAC IP they want, just need to download to FPGA?  

1. These 2 ports used for EtherCAT(mainly? Only?) or normal TCP/IP?  
2. Is there some app/driver/test that shows how to use it?  

   --- Quote End ---    Hi,  You can download from Altera website the support package for that board (latest is 13.0 SP1). ftp://ftp.altera.com/outgoing/devkit/13.0/cyclonevsx_5csxfc6df31es_soc_v13.0.0.1.exe (~ 1.4 GB!)  Under \examples\fpga_dual_ethernet\ you can find two reference designs.  Regards,  Zs.V.

[Altera_Forum]

Hi, there's no such file in the Ftp SITE, could you help to check if it is put there? 

Also, is there some document that described the FPGA MAC?

[Altera_Forum]

Hi, 

 OK, there is a problem with my link insertion. Now corrected. However you can always find the latest kit installation package at: http://www.altera.com/products/devkits/altera/kit-cyclone-v-soc.html  On the FPGA portion the usual TSE_MAC integrated into the QSys design. I suggest to see the TSE MAC and Reneseas chip documentations for further details.  Regards,  ZS.V.

[Altera_Forum]

Thanks for your help.

[Altera_Forum]

--- Quote Start ---  I want to get some information about how to support the "10/100 Ethernet (FPGA)". But I do not searched enough information except below:   10/100 Ethernet (FPGA) The development board supports an RJ-45 10/100 base-T Ethernet using an external Renesas uPD60620 PHY. This PHY supports EtherCAT, Ethernet IRT and DLR features using 3rd party MAC IP. The PHY-to-MAC interface employs MII connection using four data lines at 25 Mbps each for a connection speed of 100 Mbps.   And I have some questions as below:  

1. What is the MAC of the 10/100 Ethernet (FPGA)? 

 . It seems using 3[SUP]rd[/SUP] party MAC IP. But what is it? Is there some manual? . Is the MAC a hard CORE integrated into FPGA so that it cannot be changed or customer can use any MAC IP they want, just need to download to FPGA?  

1. These 2 ports used for EtherCAT(mainly? Only?) or normal TCP/IP? 
2. Is there some app/driver/test that shows how to use it? 

   --- Quote End ---     Hi, Were you able to successfully use the TSE IP core for Ethercat master? How is the performance? thanks