I have a question about HOW to connect the interface between the Arria II GX Transceivers and True CML clock/data delay chips (like NB6L295M) correctly.
Because the 1.5V-PCML(pseudo current mode logic), which is the IO standard of Arria II transceiver buffer, is not discribed clearly in Altera Hand book, I only got the information that the output common mode voltage (Vocm) is 0.65V(transmitter).
But, I don't know what the output differential voltage (Vod) is and how to teminating with the CML receiver. In common CML termination,
we should terminate both transmission line with 50 ohm to vcc(2.5v or 3.3v). Using this temination will make a high quiescent current about 26.5mA(3.3-0.65/100ohm) or 18.5mA(2.5-0.65/100ohm), I think it will damage the FPGA IO buffer. So I want to ask how to terminate with the CML interface correctly and safely?
Many thanks, hdjun.
