I try to communicate with a Micron Falsh attached to Arria10 FPGA with Generic Serial Flash Interface IP Core.
The part number of Flash is N25Q256A11E1240.
In my FPGA design I reset the IP Core then read CSR, which I expect to get the default values of CSR.
The following picture is a screenshot of stp, the capture clock is IP_CLK that drive the IP, currently the frequency is 100MHz.
Here are my questions:
1. I think the CSR is located in FPGA, reading CSR doesn't need to access Flash, why the qspi_pins_ncs is driven low when the FPGA starts a read CSR operation? Also the qspi_pins_data and qspi_pins_data toggle, indicates the data output from Flash.
2. According to the user guide, qspi_pins_dclk should be a division of IP_CLK, why the waveform of qspi_pins_dclk is continuous high?
3. Why the value of avl_csr_rddata isn't the defalut value when avl_csr_rddata_valid is high? I don't write anything into CSR, and I think the IP Core should output default values.