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RAM Operation on FPGA ??

Altera_Forum
Honored Contributor II
1,174 Views

Hi, 

 

I have created a Dual port RAM of width 10 bits and just 2 locations using the MegaWizard Plug In manager. It generates a certain code for the RAM with a main module named ariz. I modify the code, create another module(ram) and use the created module(ariz) in my ram module.  

 

The code is as follows : 

 

module ariz ( 

clock, 

data, 

rdaddress, 

wraddress, 

wren, 

q); 

 

input clock; 

input [9:0] data; 

input [0:0] rdaddress; 

input [0:0] wraddress; 

input wren; 

output [9:0] q; 

`ifndef altera_reserved_qis 

// synopsys translate_off 

`endif 

tri1 clock; 

tri0 wren; 

`ifndef altera_reserved_qis 

// synopsys translate_on 

`endif 

 

wire [9:0] sub_wire0; 

wire [9:0] q = sub_wire0[9:0]; 

 

altsyncram altsyncram_component ( 

.wren_a (wren), 

.clock0 (clock), 

.address_a (wraddress), 

.address_b (rdaddress), 

.data_a (data), 

.q_b (sub_wire0), 

.aclr0 (1'b0), 

.aclr1 (1'b0), 

.addressstall_a (1'b0), 

.addressstall_b (1'b0), 

.byteena_a (1'b1), 

.byteena_b (1'b1), 

.clock1 (1'b1), 

.clocken0 (1'b1), 

.clocken1 (1'b1), 

.clocken2 (1'b1), 

.clocken3 (1'b1), 

.data_b ({10{1'b1}}), 

.eccstatus (), 

.q_a (), 

.rden_a (1'b1), 

.rden_b (1'b1), 

.wren_b (1'b0)); 

defparam 

altsyncram_component.address_reg_b = "clock0", 

altsyncram_component.clock_enable_input_a = "bypass", 

altsyncram_component.clock_enable_input_b = "bypass", 

altsyncram_component.clock_enable_output_a = "bypass", 

altsyncram_component.clock_enable_output_b = "bypass", 

altsyncram_component.intended_device_family = "cyclone ii", 

altsyncram_component.lpm_type = "altsyncram", 

altsyncram_component.numwords_a = 2, 

altsyncram_component.numwords_b = 2, 

altsyncram_component.operation_mode = "dual_port", 

altsyncram_component.outdata_aclr_b = "none", 

altsyncram_component.outdata_reg_b = "unregistered", 

altsyncram_component.power_up_uninitialized = "false", 

altsyncram_component.read_during_write_mode_mixed_ports = "dont_care", 

altsyncram_component.widthad_a = 1, 

altsyncram_component.widthad_b = 1, 

altsyncram_component.width_a = 10, 

altsyncram_component.width_b = 10, 

altsyncram_component.width_byteena_a = 1; 

endmodule 

 

module ram (clock_27, sw, ledr); 

 

input clock_27; 

input [9:0] sw; 

output [9:0] ledr; 

 

ariz vj1(clock_27, 10'b1111111111, 1'b0, 1'b0, 1'b1, ledr); 

endmodule  

 

After compilation of the above code, its software simulation is right : i get 1111111111 at the output port. When I burn the code onto the FPGA, I am not able to write data into the RAM and read it on the FPGA's output LEDs. I do not get an output 1111111111 on my LEDs. What is the error in the code? Could someone help me with the right modification i need to make ? 

 

:confused:
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2 Replies
Altera_Forum
Honored Contributor II
269 Views

Have you run the simulation? what kind of LED's you have? are they common cathode or common anode type? 

Try loading data 1111100000 and check and see if that works for half of the LED's.
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Altera_Forum
Honored Contributor II
269 Views

Thanks for the reply, Altera Guy. The program I'd compiled actually worked on the FPGA too. It didn't work earlier cos I didn't include the the .csv Assignment File in assignments Menu but had included it in add/remove files from project.

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