RGMII toi SGMII Bridge

[Altera_Forum]

Team I am looking at Cyclone V SoC and need ethernet over backplane with 1588. The default hard Macro on the SoC seems to be RGMII does anyone know of a reference to feedback into the FPGA fabric either internlly or pin feeding pins back to bridge this to SGMII more suitable for backplane transmision? I am trying to avoid an extra phy.

[Altera_Forum]

Do you have transceivers available on the part? It should be fairly straightforward to transfer the 8b data between the two interfaces, you'll just need a fifo to compensate for the clock rate differences. There are LVDS/serdes interfaces, but I don't believe the CV supports up to 1.25Gbps?