RMII Mode Selection / Strapping CYCLONE III

[Altera_Forum]

Hi, 

I am working in ALTERA CYCLONE III . I have designed a module with the following NIOS II Processor + Custom Ethernet MAC working in RMII Mode + SSRAM. The Ethernet PHY used in this FPGA is DP83848C. Since I am working with a custom Ethernet MAC with RMII Mode , I have to configure the PHY to RMII. Referring the Spec of DP83848C PHY,we can select RMII mode by strapping mechanism.To do so , RX_DV/MII_MODE pin of DP83848C has to connected to VCC through a external 2.2K ohm Resistor.Whether we can configure some registers to make this selection in the CYCLONE III or we have make some external connections ?    Please Note : See the Attached PHY Document  

[Altera_Forum]

The weak pull-up option on a Cyclone III is too weak for your Phy (it is 7k Min at 3.3V) so you must have an external pull-up.

[Altera_Forum]

Hi , 

 Thanks for the Info . Could be please explain in detail why its not possible ( How you identified the specifications you mentioned ? ) I am having CYCLONE III Eval Board . How to connect external pull - up ?    Regards, Jagadeesh.B

[Altera_Forum]

The information is on page 9 of the datasheet (http://www.altera.com/literature/hb/cyc3/cyc3_ciii52001.pdf). 

If no footprint is available on the PCB to put the pull-up it may be tricky to add. See if you can access the PHY pin or a via connected to the signal. It may be easier to adapt your design to MII instead of RMII.

[Altera_Forum]

hi. 

i have a question, whether nios can be design to rmii. i know, tsw only has mii. gmii,rgmii.

[Altera_Forum]

you can use the TSE in MII mode and write your own wrapper to convert MII to/from RMII

[Altera_Forum]

how can i do it ,could you give me some helps? 

thanks

[Altera_Forum]

Basically you can do it with a state machine. On a MII interface you transfer 4 bits on a 25MHz clock, whereas on an RMII interface you transfer 2 bits on a 50 MHz clock. You can put a state machine in the 50MHz clock domain that processes the high bits on every other cycle and the low bits on the next ones.

[Altera_Forum]

To Daixiwen:thank you for your reply,but I have a question.When using the IP 192.168.0.67,the system gives the INFO:PHY[-66.-17]-speed=unknown,duplex=half.And when using the IP 219.245.66.185,the system gives teh INFO : PHY[0.0] - Speed = 1000, Duplex = Full.I don't know the reason.Does it have sth to do with network segment? 

here is the detail: Running... INFO : TSE MAC 0 found at address 0x00002000 INFO : PHY National DP83640 found at PHY address 0x01 of MAC Group[0] INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0] INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link... INFO : PHY[0.0] - Auto-Negotiation PASSED INFO : PHY[0.0] - Checking link... INFO : PHY[0.0] - Link established INFO : PHY[0.0] - Speed = 1000, Duplex = Full Waiting for link...OK IP address: 219.245.66.185 IP netmask: 255.255.255.0 IP gateway: 219.245.66.254 UDP Dest IP address: 219.245.66.200   Running... INFO : TSE MAC 0 found at address 0x00002000 INFO : PHY National DP83640 found at PHY address 0x01 of MAC Group[0] INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0] INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link... INFO : PHY[0.0] - Auto-Negotiation PASSED INFO : PHY[0.0] - Checking link... INFO : PHY[0.0] - Link established INFO : PHY[0.0] - Speed = 1000, Duplex = Full Waiting for link...OK IP address: 192.168.0.67 IP netmask: 255.255.255.0 IP gateway: 192.168.0.1 UDP Dest IP address: 192.168.0.68 INFO:PHY[-66.-17]-speed=unknown,duplex=Half  another doubt is:when I got the INFO posted above,Could I ensure my interface converter mii to rmii worked! waiting for your reply,thank you!

[Altera_Forum]

In both cases you have this line 

--- Quote Start ---  INFO : PHY[0.0] - Speed = 1000, Duplex = Full  --- Quote End ---   which indicates that the MDIO communication with the PHY chip is working correctly. I have no idea where this line  --- Quote Start ---  INFO:PHY[-66.-17]-speed=unknown,duplex=Half  --- Quote End ---   is coming from but -66 and -17 are obviously bogus so it's probably a software crash that leads the function to be called with wrong parameters. Anyway, this just shows that the MDIO is working. It's using different signals than the MII or RMII lines, so this doesn't say if your RMII interface is working correctly. If you don't see any network traffic you should check on both sides (MII and RMII) with SignalTap is you see any packet coming or going from the Ethernet interface.

[Altera_Forum]

Dear daixiwen: 

I can't get the package by using the wireshark(tools for capture pcakage),How can i do it,could you give me some advice?By the way ,may I ask a question:Do you konw anyone who successed by using the PHY RMII interface connected mii interface which supply by TSE! By the way ,could you understand chinese language? waiting for your reply,thank you!

[Altera_Forum]

I did, but unfortunately I can't share the code. IIRC it wasn't that hard to do. I suggest to use signaltap on your conversion component to see what happens. 

And I'm sorry, I don't understand Chinese.

[Altera_Forum]

Dear daixiwen: 

thank you for your reply,and I have some problems to: I can't ping the board,and I used the signaltap to test the mdio and phy_RXD(you can get info from attachments),the signatap process always waiting for trigger,did I miss sth? here is the nios debug detail: Running... INFO : TSE MAC 0 found at address 0x00002000 INFO : PHY National DP83640 found at PHY address 0x01 of MAC Group[0] INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0] INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link... INFO : PHY[0.0] - Auto-Negotiation PASSED INFO : PHY[0.0] - Checking link... INFO : PHY[0.0] - Link established INFO : PHY[0.0] - Speed = 1000, Duplex = Full Waiting for link...OK IP address: 219.245.66.185 IP netmask: 255.255.255.0 IP gateway: 219.245.66.254 UDP Dest IP address: 219.245.66.112 OK.  waiting for your reply,thank you!

[Altera_Forum]

What are you triggering on? 

What is the phy_rx_err signal and what is it connected to on the PHY side? If it is the combined rx enable/error, I find it strange that it isn't asserted when you see changes on the RX[0] and RX[1] signals... it could be a bad connection to the PHY.

[Altera_Forum]

Dear Daixiwen: 

For many days passed,my problem still going on,I use the LWIP+TSE+DP83640+rmii to do the project!  Here is my board information, I use the example from the forum, the webside http://www.alteraforum.com/forum/showthread.php?t=23787  trying to ping the board,I get the information: Running... INFO : TSE MAC 0 found at address 0x00004000 INFO : PHY National DP83640 found at PHY address 0x01 of MAC Group[0] INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0] INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link... INFO : PHY[0.0] - Auto-Negotiation PASSED INFO : PHY[0.0] - Checking link... INFO : PHY[0.0] - Link established INFO : PHY[0.0] - Speed = 1000, Duplex = Full Waiting for link...OK Waiting for DHCP IP address...@����������������������������������������������� can't get the DHCP IP address,I debug step by step,I found my software jump to this line  if(ethernetif->lwipRxCount == 0)  return NULL; in function low_level_input(struct netif *netif). the mdio detect correctly also the mac rx_clk tx_clk,but rxd and txd t detect anything ! the attachment is my board information,maybe you can give me some help! best wishes to you,thank you!

[Altera_Forum]

Did you check my questions?

[Altera_Forum]

yeah,my phy can work on rmii module,the phy_rx_err signal combined rx enable/error,but I'm not sure my rmii to mii interface work normally！

[Altera_Forum]

Did you try to trigger on the combined rx enable/error signal? If this signal never goes to 1 then the problem isn't in the rmii to mii interface, but before that. Either the PHY isn't connected correctly to the FPGA, or the PHY itself doesn't receive anything, is badly configured or broken.