RTL Sequence creation

[Altera_Forum]

Hi there people, I'm studying VHDL programing and i'm getting stuck on this question and i have a examination coming up soon, so i'm stressing a little.  

 My question is.  A 5-bit signed number (two complement) is read into a machine on the push and release of an active low ley. negative values are converted into positive magnitude form and even valued number are ignored. When 8 odd valued numbers have been entered, the machine displays the average value of the set along with a ready indicator. The machine then halts and repeats the process on activation of an asynchronous master reset of active low.    COuld someone please help me write a register transfer language sequence. Could you please show me step by step so i understand where is start and the process. I would love to be shown how its done and not just here the answer so i get the question.   kind regards

[Altera_Forum]

Instead of just asking someone to do your homework for you - why not have a go yourself and ask questions on the bits you're stuck with.

[Altera_Forum]

I'm not asking anyone to do my homework, i would love to get a helping hand to show how i would go about this question and where to start as i'm new to VHDL. A breakdown would be awesome

[Altera_Forum]

1. Find VHDL and digital logic textbook or your class notes. 

2. Study them 3. get a text editor 4. write VHDL in text editor to learn VHDL  For your problem, when youve completed the steps above:  1. Draw an architectural diagram of the circuit. 2. Write down the detail of how it will work. 3. Write VHDL.  When you've attempted the above, please ask more questions.