RTL of design is different from expected

[Altera_Forum]

I would like to implement a freq divider by using clock enable method(clock enable signal connect to every enable pin of register in design).  

 however, when i write the verilog code  e.g "if (clock_ena== 1 && function_ena == 1) ... non blocking statement)",   the RTL viewer shows that the architecture is changed(the enable pin of register is not connected).  May i know how to ask the compiler to design the way that i expected? It is because i have difficulty on write time quest constrait.   thanks

[Altera_Forum]

The clock enable function is usually implemented in the combinational logic. The reason for it is simple: None of the recent Altera FPGA families has a dedicated clock enable input at it's core registers, check the device manuals.

[Altera_Forum]

noted. thanks

[Altera_Forum]

FvM, the problem i faced is the name of output of comb logic is the name synthesized by QII. I cant constraint multicycle path on the every module i have 1 one shot. Any idea on it? Or this is the disadvantage of using clock enable method?

[Altera_Forum]

Try this 

 (* keep = 1 *) wire my_clk_en = clk_ena && function_ena;  always @ (posedge clk) begin  if(my_clk_en) begin  ...  end end   This way you'll be able to find the my_clk_en in TQ with get_keepers.

[Altera_Forum]

rbugalho, 

 If doing like this, it will lost the function of one input signal. As we know, when clk_ena is low, output will maintain the previous data. When function_ena is low, output will be low as well.  Anyway, i have tried the method u proposed. I fail to find the my_clk_en. Besides, the enable pin of register is not connected to anything