Dear Intel Support Team,
I hope this message finds you well.
I am currently conducting IBIS simulations for the Cyclone V FPGA, specifically for the part number 5CGXFC9C6F23, and I have a few questions regarding the IBIS model definitions provided on your official website.
Upon reviewing the IBIS file available at the following link:
https://www.intel.co.jp/content/www/jp/ja/support/programmable/support-resources/board-layout/ibs-ibis-index.html
I noticed that several I/O buffer models appear to have identical definitions despite having different names. For example:
- "lvcmos_rtpio_d2s1" and "lvcmos_rtpio_d16s1"
- "lvcmos_rtpio_d2s1_p" and "lvcmos_rtpio_d16s1_p"
These models seem to be completely identical in terms of their IBIS definitions, which raises concerns about their accuracy and applicability for simulation purposes.
I would like to ask the following:
- Are there any updated or revised IBIS model files for Cyclone V released after March 20, 2020, which is the last modification date shown on the website?
- Among the available models, which ones are considered accurate and appropriate for simulation, particularly for the I/O standards listed below?
The I/O standards I plan to use are:
- 3.3V LVCMOS (lvcmos_*)
- 3.3V LVTTL (lvttl_*)
- SSTL-135 (sstl135_*)
- Differential SSTL-135 (dsstl135_*)
Your guidance on this matter would be greatly appreciated, as it will help ensure the validity of our signal integrity simulations.
Thank you very much for your support.
Best regards,
Ryusuke YOKOYA
