Regarding an 8bit down counter

[Altera_Forum]

hi, 

 i designed an 8bit down counter by referring the "advanced synthesis cookbook". but the RTL viewer is showing a MUX, an adder and an 8bit register to represent this counter. is this correct? should i not expect a counter block instead? implementing an adder for a counter does not make sense to me. Let me know your thoughts regarding this.  thanks,  Sumanth

[Altera_Forum]

--- Quote Start ---  hi,  i designed an 8bit down counter by referring the "advanced synthesis cookbook". but the RTL viewer is showing a MUX, an adder and an 8bit register to represent this counter. is this correct? should i not expect a counter block instead? implementing an adder for a counter does not make sense to me. Let me know your thoughts regarding this.  thanks,  Sumanth  --- Quote End ---    hi Sumath,  how do you are the counter descript ? I assume you wrote something like this (Verilog)  counter <= counter + 1 , that's you Adder  Maybe you have defined a reset :  if (reset) counter <= 0; else counter <= counter + 1 ; that's maybe the MUX  Adder and Mux is ok for a counter.

[Altera_Forum]

hi, 

 i dont agree with the argument that its ok to implement a counter with a mux, adder and a register. an adder is a data path element and it will induce more delay in my design. morever, an adder will unnecessarily consume more logic elements. To avoid this, i read somewhere to use the "lpm_counter" which will make my design incompatible with other vendors. Plz, can anyone suggest a way to work around this prob?  thanks in advance,  sumanth

[Altera_Forum]

A counter can be implemented using a T flip-flops chain with the output (q) of previous clocking the next. This works, but has several clock skew problems related with the multiple clock domains introduced. 

 This is the reason that is preferred the solution using the adder and register.  lpm_counter simply uses mux and counter efficient versions by manipulating the logic cells (lcell) directly.    Check the RTL with RTL viewer.

[Altera_Forum]

And don't put too much emphasis on the RTL viewer. I'm not even sure if it has a "counter" block. It may look like an adder(since a counter is just an adder with a constant of 1 on one side). The main concern is that after the RTL gets synthesized, what does it look like? You'll want to use the Technology Map View for this. It's much more difficult to read, since it's at a lower level. The other thing to look at is the resource usage, which is really the most important thing. If your 8-bit counter uses 8 logic elements(or something different dependint on the family you're targeting), than that's as compact as it gets. Whether the RTL viewer shows you an adder and a mux, or a counter, is just an intermediate step.