Regarding custom logic issue in sopc

[Altera_Forum]

I am running software example given with nios II that prints "Hello world". It uses nios CPU, onchip memory, led pio, jtag. I have generated my own custom logic and connect to these component using SOPC and generated modelsim files. Then using Nios II it generate onchip_memory.dat file that stores instruction. I run simulation and it works properly but i want that Nios CPU generate consecutive reads writes and burst reads writes with the address that i provide not the address or read write instructions in that example.  

Basically i want to test my custom logic with consecutive read writes and bursts.   How it can be done ? I have to generate my own instruction file or can i do it in sopc?

[Altera_Forum]

Is your problem creating any reads to your peripheral, or making Nios do burst accesses?

[Altera_Forum]

Hi phil, 

Yes i want to do burst access from nios. Right now nios is doing reads and writes but not busrts.   Pankaj

[Altera_Forum]

I think that the Nios cache will do bursts. Have you tried using the Nios with a data cache, then filling it with data and flushing the cache line by hand?

[Altera_Forum]

No i haven't try yet. For this i have to write instructions in Nios IDE or some settings in SOPC. Can i also set burst length and consecutive reads writes.  

 Thanks for quick reply.

[Altera_Forum]

There isn't a way to configure the burst length that the cache uses when doing a write back. 

 If you are trying to do anything more than a simple smoke test, then a RTL testbench is going to be the best way forward.

[Altera_Forum]

You can't really force the NIOS to do bursts. You can configure it to do bursts and you may be able to take advantage of the data cache to get it to do bursts.  

 If you need some high performance data transfer then you should use a DMA controller; either your own custom logic or one of the Altera DMA controllers.  Jake

[Altera_Forum]

hi, 

I am trying to find some example regarding burst from CPU but couldn't find. Can i have some examples in which we can configure cache to get bursts

[Altera_Forum]

Just click "enable bursts" in the CPU configuration. 

But in my opinion it's better to use a SGDMA. You have a better control on the kind of transfer that you want to do and the length of the bursts.

[Altera_Forum]

Hi, 

Thanks everybody for your support, I am able to generate bursts data from nios II, by using data cache but i also want to customized instructions from nios II, for example i want nios II to do consecutive reads and writes. For this i want to change avalon 'write' and 'read' signals such that during one cycle it should write and in another cycle it should read. How it can be done ? For this i have to write my own custom instruction or there is some option in nios II to do this task.  Pankaj

[Altera_Forum]

You can't do that with a custom instruction. You'll rather have to create your own component with an Avalon master interface and have it do the consecutive read and write accesses.