Registers in series - why clock time delays?

[Altera_Forum]

Hello people! 

 Can someone please explain why is it that there is one clock delay to transport input to output when I have two registers (Flip Flops) in series? I mean the transport time form the input of the first to the output of the second. Does this have to do with metastability, setup and hold times? Is the situation exactly the same inside the FPGA? A code visualizing two registers in series is translated exactly to the equivalent digital circuit? What should someone expect as far as the time clock delays are concerned?  Thanks

[Altera_Forum]

thats what registers do... 

 if the startsetting of the registers is 00, then we have at   time 0 the value 00 if we set at time 1 register 1, then we have time 1 the value 10 and of we reset the register 1 at the next clock, then we have time 2 the value 01 and so on...  i hope you get it, if you have detailed questions about that, do not hesitate to ask them in a detailed way.

[Altera_Forum]

Maybe I wasnt so clear and precise. 

  So we have two generic flip flops in series. This means that they share the same clock and the Q1 of the first is connected to the D2 of the second. Input is D1 and output is Q2. Why do I need two cycles to push the input D1 to the output Q2?  I used the term registers because i may have the smae thing 16 times in parallel  Regards

[Altera_Forum]

you need 1 clock that the input D1 is on the output Q1 , what is wired connected to the input D2 and then you need another clock, that D2 is at Q2. 

 That is what and how Registers(FFs) do...  And if its that what you see, than your registers work properly!!!

[Altera_Forum]

Thanks for your answer! I know that though. 

 My question was why. Does this have to do with metastability, setup and hold times?

[Altera_Forum]

it is related to the physic of a flipflop.