Registers remover During synthesis

[Altera_Forum]

Hello; 

I have some Registers remover During synthesis because a lost fan out. But Iam sure that these registers followed by a compinational logic then another registers(system pipeline), here are my questions: 1- Does the synthesis fail to know those logics that follow these registers, so it mark them as lost fan-out? 2- During the simulation(with modelsim-altera-edition), I found these registers and it have an effect on the system latency. How was it removed and still simulated?

[Altera_Forum]

Do any of your device output signals (pins) depend on these registers or the combinational logic they drive? I suspect not. They may be part of a pipeline. However, if none of the FPGA's output signals depend on them, Quartus will remove them. Quartus will only remove registers whose output signals are not used - and it's very good at determining whether or not they are used - i.e. whether they're required. 

 ModelSim may well show you the latency. However, ModelSim won't remove any registers. What ModelSim shows you isn't necessarily representative of the behaviour of the code you've run through Quartus.  So, I suggest you revisit your code and how you've connected it up at your top level.  Cheers, Alex

[Altera_Forum]

Thanks Mr Alex for ur reply; 

The removed registers located in a pipeline. It feed a combinational logic of at minimum (3 xor + 1 And ) operations in cascade then the destination register. Is these loads are not enough to make fan-out signals, so that it is removed.

[Altera_Forum]

ouh... you can try use vhdl "keep" synthesis attribute if you project in vhdl/try find template in quatus text editor. 

also you can locate your removed register and make "preserve" assignment for it.

[Altera_Forum]

Hello a4atmel, 

 The quartus tool automatically removes the unused registers during the synthesis process, that is why your registers are getting removed. If you want to preserve those registers please go through the link below   For verilog http://quartushelp.altera.com/15.0/mergedprojects/hdl/vlog/vlog_file_dir_noprune.htm  For VHDL  http://quartushelp.altera.com/14.1/mergedprojects/hdl/vhdl/vhdl_file_dir_noprune.htm