Is it acceptable to use a cyclone v user I/O pins to program the flash memory containing configuration for the cyclone v. This would be muxed in after power-up/configuration with the DCLK and other reserved I/Os and provide for a way to program through the flash (EPCS device) through the FPGA. Are there downsides to doing it this way, such as power-up problems? I was going to put a heavy pulldown/pullup on the mux select line so that this could only occur in user mode. Alternatively, has anyone used the altera remote update ip core w/o a NIOS? Could I just design my own state machine/processor to communicate with the remote update ip?
You don't need to use I/O to do this. Cyclone V offers you access to the EPCS pins from your logic. Yes, you can just write your own logic to access/program the EPCS device if you wish.Alternatively, you can use the altera serial flash loader ip core (https://www.altera.com/products/intellectual-property/partner-page/serial_flash_loader.html). Cheers, Alex