Remote update of MAX10 device over I2C

[HimakarAl]

Hi,

My device is 10M08DAF256C7G using on a custom board. I am planning to update this FPGA over I2C remotely. This process will be initiated by an micro controller.

After going through some documents on this, I could find that this can be achieved using these following IPs as per the below block diagram

"I2Cslave_to_AvalonMM", " NIOS" and "On-chip Flash".

Now my main concern is

1) Whether NIOS is actually required? Can't we connect directly the "I2Cslave_to_AvalonMM" to the "On-chip Flash" (As both are having Avalon MM as interface) ?

2) If Nios is required, What will be the role of NIOS over here?

3) Also Which NIOS is preferable NiosII or NiosV/c ?

4) If NIOS is to be used, then is this connection is proper?

5) If the connection is proper, From where NIOS will get the data that is to be decoded and written to the On-chip flash.

Looking forward to any guidance.

Thanks and Regards,

Himakar

[NurAiman_M_Intel]

Hi,

To answer your question whether NIOS is required when using Remote update over I2C with FPGA,

Yes, NIOS is required. NIOS II will act as controller as FPGA need a specific controller when doing remote update over I2C.

You can refer to below userguide for more information on I2C remote update:

https://www.intel.com/content/dam/support/us/en/programmable/support-resources/fpga-wiki/asset03/user-guide-151.pdf

There is also I2C remote update design example for reference:

https://www.intel.com/content/www/us/en/design-example/714746/intel-max-10-fpga-i2c-remote-system-update-design-example.html

Regards,

Aiman

[NurAiman_M_Intel]

We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

[FvM]

Hi,
sorry for the late reply. NIOS is not required. You can also design a pure HDL I2C to on-chip flash controller interface. Unfortunately there's no ready-made example available from Intel.