Reset_ip for stratix GX development board

[philcj]

Hello, could some one help me rectifying the issue with the usage of reset IP with Intel Stratix FPGA development board.

I am trying to understand how does this IP function when my design have an asynchronous reset. I have tried to create an 8-bit counter. I have uploaded the design files. The design is completely compiled. I have used a clock of 200MHZ(clk_in). However, the reset IP operated at 100MHZ internally. I have used a synchronizer chain to address the CDC issue here. Kindly check my design. Even though the design is getting compiled, DRC report still shows the rule violation CDC-50012 Multiple clock domain driving a synchronizer chain.

Design Assistant Document:
CDC-50012
Tags: synchronizer

Description:
A synchronizer chain is accepting data from multiple clock domains at once. A synchronizer chain can only synchronize data from a single clock domain.

Recommendation:
Either synchronize each incoming clock domain with different synchronizer chains in the same destination domain, placing any required combination al logic in the destination domain, or cascade the clock crossings with transfers from one source clock domain at a time.

Violation Fields Description:
'From' : Registers that launch data in a CDC transfer
'To' : Registers that latch data in a CDC transfer
'From Clock' : CDC transfer source clock(s). These clocks drive the "From" registers
'To Clock' : CDC transfer destination clock(s). These clocks drive the "To" registers
'Reason' : The reason why a transfer is considered a CDC

From : dut_test|s10_user_rst_clkgate_0|lsm_gpo_out_user_reset~internal_clock.reg dut_test|s10_user_rst_clkgate_0|lsm_gpo_out_user_reset~internal_clock.reg__nff

To: syn_test|reset_reg[0]

From clk: internal_clk internal_clk (INVERTED)

To clock: clk_in

Reason: Asynchronous transfer

I am unable to identify what went wrong here. I even tried to double flop the ninit_done signal before passing to the assign statement 'reset_out' (not shown in code). But this also is not rectifying the issue. If someone help me with what went wrong it would be beneficial. Thanks a lot for your time.

[Farabi]

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[Farabi]

Hello,

The Design Assistant rule CDC-50012 indicates that your synchronizer chain is being driven by signals from multiple clock domains. This violates the principle of proper CDC (Clock Domain Crossing) design, which requires each synchronizer chain to handle signals from only one clock domain.

From violation description, we can conclude that the synchronizer chain reset_reg[0] is being driven by internal_clk and its inverted counterpart (internal_clk (INVERTED)). This creates ambiguity in the source clock domain for the chain.

If your reset signal is generated in a clock domain (e.g., internal_clk) and used asynchronously in another domain (clk_in), you need to properly synchronize it to avoid CDC issues.

Please make sure the reset signal is synchronized to a single clock domain (internal_clk OR clk_in) before entering the synchronizer chain.

If internal_clk and clk_in must both contribute to the reset logic, use separate synchronizer chains for signals from each clock domain.

Example how to sync reset signal to internal_clk domain, then transfer to clk_in domain:

// Synchronize to internal_clk

reg sync_reset_internal_clk1, sync_reset_internal_clk2;

always @(posedge internal_clk or negedge async_reset)

 if (!async_reset)

  {sync_reset_internal_clk2, sync_reset_internal_clk1} <= 2'b00;

 else

  {sync_reset_internal_clk2, sync_reset_internal_clk1} <= {sync_reset_internal_clk1, async_reset};

// Transfer to clk_in domain

reg sync_reset_clk_in1, sync_reset_clk_in2;

always @(posedge clk_in or negedge sync_reset_internal_clk2)

 if (!sync_reset_internal_clk2)

  {sync_reset_clk_in2, sync_reset_clk_in1} <= 2'b00;

 else

  {sync_reset_clk_in2, sync_reset_clk_in1} <= {sync_reset_clk_in1, sync_reset_internal_clk2};

// Use sync_reset_clk_in2 in the clk_in domain

wire reset_out = sync_reset_clk_in2;

re-run the Design Assistant Report-> verify CDC-50012 violation is cleared.

regards,

Farabi