I have problems using the FPGA-HPS DRAM interface on a Cyclone V SOC device. The problem seems to be related to reset.
Sometimes the slave interface that is built-in on the HPS, came up with the waitrequest signal stuck on an asserted state. Other times it starts ok, and when it starts ok it works for the rest of the session without any problems. This suggests it is a reset problem
But the problem is that the slave interface doesn't have a reset signal. The device manual mentions each port having an individual input reset signal. But if the signal exists at the hardware, it is not exposed by the instantiation.
I am using a clock provided by my own logic on the FPGA side. It is supposed to work like this according to the documentation. But the lack of a reset signal makes me doubt about this. The HPS built-in slave interface has a clock input signal but not a reset one. Doesn't sound right.
I found this KDB article: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/embedded/2016/how-and-when-can-i-enable-the-fpga2sdram-bridge-on-cyclone-v-soc.html
It might explain the behavior I am seeing.