Ring oscillator output always high

[Altera_Forum]

Hi Folks, 

 I've built three simple ring oscillators (3, 7 and 15 NOT gates), they are connected to 3 standard I/O ports on my board (EP4CE6E22C8) but unfortunately their outputs are all high and never change state.  What am I doing wrong? Please see the block diagram and my demo project in the attachment.  Many thanks for your help in advance.

[Altera_Forum]

Hi Agentgates, 

 Honestly i have never tried to build such a design in FPGA before.  I could think of 2 concerns: 1) I am not sure if your the Quartus software could synthesis the pins properly. as there are no clk and reset or inputs. You can check compilation to see if the rtl was synthesis or if there are any part of the logic being ignored. 2) The other thing you could do is to build a simple logic either pushbutton to toggle or simple logic to drive high or drive low to see if the output pin are working. just to confirm the pin are working.

[Altera_Forum]

Ring oscillators are not easy in FPGAs. Unless you've specifically locked some of the logic Quartus is going to 'optimise' all but one inverter away. That's not going to leave much of your circuit. It's no wonder it's not oscillating... 

 Ring oscillators have been discussed on this forum before. It's worth having a good search. Look at the following post for starters: [url]http://www.alteraforum.com/forum/showthread.php?t=48727 (http://www.alteraforum.com/forum/showthread.php?t=48727)[/URL]  It also refers to an Altera Wiki page (Altera Wiki seems to be down at present) which I've referred to before. Very useful.  Cheers, Alex

[Altera_Forum]

Thanks for the suggestion and the link. I think that's the problem, the lack of delay. I'll be offline for awhile but as soon as I get back to the dev board I'll give it a shot again.