Ris/fall time?

[Altera_Forum]

Hello, 

I am developing a simple test board for a cyclone FPGA (EP2C8T144). It is my very first FPGA project, and I want to build my own FPGA board.   Now, my question is: Which rise and fall times can I expect on any I/O pin of the FPGA? I am not using LVDS. I just use simple 3.3V LVCMOS. The problem is, that there will be reflections on longer tracks on the PCB, if the rise time is too short. How can I calculate the maximum allowed track length if I know the driver strength of the I/O pin (4 mA)?   Hope, somebody can help me! This would be very great. Thanks a lot in advance and excuse my bad english (I am a student in Switzerland) :D

[Altera_Forum]

I suggest you to avoid connecting the FPGA output pins to input pins of the device that you are driving. Put a small series resistor (22ohm or 33ohm) in every track and you will avoid this kind of reflection problems independently of the track length.

[Altera_Forum]

Hello OrchestraDirector, 

thanks for your answer. The device which I am driving with the FPGA is an ARM7 microcontroller (the FPGA is attached to the micro's memory bus). How long can I make the trace length, if I don't put any resistors in the tracks? Longest track is ~25 mm. Will this work if I program driver strength to minimum? I don't need very fast I/O (I'm working with low frequencies).

[Altera_Forum]

Hi, if your frequencies are low enough (let's say under 50MHz) you can go on without series resistors also with 25mm, with higher frequencies a resistor array of 22ohm is recommendable.

[Altera_Forum]

Dear OrchestraDirector, 

thank you a lot! My ARM works with 72 MHz, but the external data bus is slower. So, I think this could work ;) Is it maybe possible to use longer tracks than 25 mm? And is it correct that only the Pins, which are outputs on the FPGA, need a series resistor?   Thank you for your help!

[Altera_Forum]

Yes, correct, but be careful to place the resistor array next to the destination pins, which are in your case the microcontroller input pins.

[Altera_Forum]

Okay. What if some pins are bidirectional (like the data bus from the micro to the FPGA) ? place the resistors anyway near the microcontroller?

[Altera_Forum]

If you can, it is advisable to use a separate resistor array for the unidirectional signals (near the destination pins) and a resistor array for the bidirectional signals, which can be placed wherever you like between the pins.

[Altera_Forum]

Some suggestions haven't been clear to me, so I like to mention, what I would do. 

 Basically I use a series resistor a the driver, that means at both end for a bidrectional signal. On chip series termination respectively selecting a low current strength (another name for the same thing) with FPGA can save external resistors in most cases.  A typical single ended trace impedance on a multilayer PCB is in the 50 to 90 ohms range. You can use calculation tools to determine the nominal impedance for your board. So if you have a digital output with high current strength (e. g. a logic device with 10 to 20 ohm output impedance) a series resistor of 33 to 68 ohm would be a suitable choice.

[Altera_Forum]

Have to agree with FvM here. I have generally used a series terminaton at source and not had any issues. On Chip series termination is a good idea. 

 This article is pretty good  http://www.ultracad.com/mentor/mentor%20termination%20placement.pdf  Rgds

[Altera_Forum]

@FvM and vernmid: 

Thank you very much! That's exactly what I wanted to know :-) And this pdf article looks interesting. Hmm, does Cyclone II support on-chip termination? I found this feature only in Cyclone III devices.

[Altera_Forum]

--- Quote Start ---  Hi, if your frequencies are low enough (let's say under 50MHz) you can go on without series resistors also with 25mm, with higher frequencies a resistor array of 22ohm is recommendable.  --- Quote End ---      --- Quote Start ---  My ARM works with 72 MHz, but the external data bus is slower. So, I think this could work  --- Quote End ---    Signal integrity is a function of the frequency content of the signal edge rate for each separate signal transition regardless of the clock frequency or how often the data signals toggle. Even if a signal toggles just once, the noise will depend on the edge rate and the squareness of the corners at the start and end of the transition. Clock frequency is relevant to the extent that a longer clock period allows more time for reflections to settle out before the data is registered at the destination, but even with a slow clock frequency avoid excessive voltages from noise that exceed the device specifications. Avoid noise on clocks of any frequency so that the receiving device won't interpret ringing as false clock edges.  There are more termination methods than just series resistors. Some FPGA device families offer more than one method, and you could implement any method external to the FPGA if there is room on the board. You can find documentation on the web beyond the Mentor article already provided by searching for things like "parallel termination", "Thevenin termination", and "diode termination" in addition to "series termination". You should be able to find recommendations for bidirectional signals.  There are additional techniques that can help signal integrity like routing a signal near a ground plane or adjacent to a ground trace on the same layer to provide a good return current path for the signal with minimal area for the entire current loop.     --- Quote Start ---  On chip series termination respectively selecting a low current strength (another name for the same thing) with FPGA can save external resistors in most cases.  --- Quote End ---    The assignments you have available for this depend on the device family. Any of these assignments can be set in the Assignment Editor. Most or all of them are also available in the Pin Planner, but you might have to use "Customize Columns" on the "All Pins List" right-click menu to enable them to be displayed. The assignments are called "Current Strength", "Termination" for families like Cyclone II and "Input Termination" and "Output Termination" for some families, "Slew Rate" or "Slow Slew Rate" (not for Cyclone II), and possibly others.