Rise/fall time for general purpose outputs in MAX10 devices

[ValeriT]

Hello, I'm trying to find the rise/fall time spec for the general purpose outputs of MAX10 devices, but these data are unavailable in the data sheet. How I can know what is their typical value?

Thanks

[KhaiChein_Y_Intel]

Hi,

You may check this in Timing Analyzer by clicking on Reports >Datasheet > Report Datasheet.

Thanks

Best regards,

KhaiY

[ValeriT]

Thanks for reply, but I understand that the datasheet refers to the setup times relating to the clock, not the rise/fall time of each specific signal itself. So, the value I see is about 5-6ns - it's definitely not the rise time I'm looking for.

Again, I refer to the transition time from low to high and from high to low, typically from 20% to 80% of the max level

I found the Input Transition Times report in the Timing Analyzer>Advanced I/O Timing - does it give me the desired number? I'm a bit confused with a word "Input" as I'm looking for the output signals' rise/fall time

Thanks,

Valeri

[KhaiChein_Y_Intel]

Hi Valeri,

The Datasheet Report has the Rise / Fall time for each of the signals. Do you see the similar report as attached?

Thanks

Best regards,

KhaiY

[ValeriT]

Hi Khai,

The data sheet report I see is slightly different - see the attachment data_sheet1. It seems to be a setup times report, not the transition times, not mentioning the fact that all the signals in this report are inputs, while I'm looking for transition times for outputs.

On the other hand, there is another report - see the attachment data_sheet2. Though they call it Input Transition times, the pins in the report are both input and output pins. Isn't it what I'm looking for?

Thanks,

Valeri

[KhaiChein_Y_Intel · Accepted solution]

Hi Valeri,

The report_datasheet creates a datasheet report which summarizes the timing characteristics of the design as a whole. It reports setup (tsu), hold (th), clock-to-output (tco), minimum clock-to-output (mintco), propagation delay (tpd), and minimum propagation delay (mintpd) times. These delays are reported for each clock or port for which they are relevant. 

The Timing Analyzer uses advanced I/O timing and board trace model constraints to model I/O buffer delays in your design. If you want to check the 10-90 Rise/90-10 Fall time, you may refer to Input Transition Times / Signal Integrity Metrics.

Thanks

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best regards,

KhaiY