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Hello! The Board of the company HiTechGlobal S5-PCIE pins RREF
transceiver banks FPGA Stratix V GX are connected to the GND through resistors 2 kom. In the recommendation of the Altera written that these pins should be connected through a resistor 1.8 kom. Can the violation of the recommendations lead to the malfunction of transceiver banks?Link Copied
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Hi,
Do you have anything new on this issue? I am using this board and having some problems with the PCIe interface. Thank you
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