CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
Success! Subscription added.
Success! Subscription removed.
Sorry, you must verify to complete this action. Please click the verification link in your email. You may re-send via your
profile.
I have created a project by loading SCFIFO megafunction generated vhdl file. When I am simulating in MODELSIM, OUTPUT DATA is not coming even when the Read pulse is enabled. Someone kindly help.
Yeah I have added the library. I am simulating .vhd file which is generated after megafunction configuration. Problem is during simulation WRITE operation is working fine for every clock. But read operation is not working when RD signal is enabled. Kindly post if you have a working SCFIFO code. I ll try to simulate that and check mine. By the way code is uploaded. If possible can you verify it.
I bet the SCFIFO is working just fine. Its your app code thats not working.
Instead of blaming the SCFIFO thats used in 1000s of projects worldwide without a problem, why not post your interface code and maybe we can help with that.
With the configuration of the FIFO you chose it will take one clock cycle after a 'rdreq' pulse for the data to show up on the output. Does your simulation code account for this?
Can you post your testbench code so that we can see what you are doing with the FIFO?
