SD/MMC controller and ACP possible?

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

SD/MMC controller and ACP possible?

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Hello,

I am trying to get the SD/MMC controller to work with the ACP ID mapper.

Everything seems to work fine if I use uncached SDRAM or OCRAM for descriptors and buffers.

But I can't get coherent access over the ACP to work.

I have successfully setup the ACP ID Mapper for dynamic configuration. This works fine with EMAC DMA as well as custom devices from the FPGA. (I also tried a static configuration for the SD/MMC controller, but this didn't seem to make a difference).

I am using the address >= 0x80000000 and tried different settings of ALT_SYSMGR_SDMMC_L3MST_ADDR.

But the SD/MMC controller refuses to access the cache.

I am surely missing some magic setting that is required for SD/MMC to ACP access to work. Maybe it is related to the AHB bridge?

Thanks,

Peter

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