SDC Constraints for Asynchronous Interfaces

[Altera_Forum]

I am trying to constrain some asynchronous interfaces which my FPGA interfaces to. I have a single FPGA clock, CLK_FPGA (period = 20ns) which clocks all logic in the FPGA. One asynchronous interface is an MRAM, and it does not have to be constrained within one CLK_FPGA period. It can be very slow. 

 First I tried the following: create_clock -name {CLK_FPGA} -period 20 {CLK_FPGA} set_max_delay 80 -from [get_ports { MRAM_RDY }] -to {CLK_FPGA} set_min_delay 0 -from [get_ports { MRAM_RDY }] -to {CLK_FPGA} set_max_delay 80 -from {CLK_FPGA} -to [get_ports { MRAM_CS_N }] set_max_delay 80 -from {CLK_FPGA} -to [get_ports { MRAM_CS_N }]  This seemed to work on some interfaces, but not on others. I am not sure why?  Then I tried the following: create_clock -name {CLK_FPGA} -period 20 {CLK_FPGA} create_clock -name {CLK_ASYNC} -period 80 set_input_delay -max 0.000 -clock {CLK_ASYNC} [get_ports { MRAM_RDY }] set_input_delay -min 0.000 -clock {CLK_ASYNC} [get_ports { MRAM_RDY }] set_output_delay -max 0.000 -clock {CLK_ASYNC} [get_ports { MRAM_CS_N}] set_output_delay -min 0.000 -clock {CLK_ASYNC} [get_ports { MRAM_CS_N}]  Again, this seemed to work on some interfaces, but not on others. I am not sure why?  Then in the paper TimeQuest User Guide, it mentioned a different method by using a virtual clock that matches the main clock, and using mutiple path constraints to specify the relaxed timing. Before I re-write my entire SDC file, does this method make sense? They would look something like this: create_clock -name {CLK_FPGA} -period 20 {CLK_FPGA} create_clock -name {CLK_ASYNC} -period 20 set_input_delay -max 0.000 -clock {CLK_ASYNC} [get_ports { MRAM_RDY }] set_input_delay -min 0.000 -clock {CLK_ASYNC} [get_ports { MRAM_RDY }] set_output_delay -max 0.000 -clock {CLK_ASYNC} [get_ports { MRAM_CS_N}] set_output_delay -min 0.000 -clock {CLK_ASYNC} [get_ports { MRAM_CS_N}] set_multicycle_path 4 -setup -from [get_ports { MRAM_RDY }] set_multicycle_path 4 -hold -from [get_ports { MRAM_RDY }] set_multicycle_path 4 -setup -to [get_ports { MRAM_CS_N}] set_multicycle_path 4 -hold -to [get_ports { MRAM_CS_N}]  Any help or clarification would be appreciated.