We are developing a project based on AXE-5 Eagle board and we are facing some issues
We need to drive some clocks and SDI signals through the FMC+ interface, we are defining some pins based in the eagle board user guide. Attached you can find our QSF file.
When we tried to compile we got the following errors, all of them have the same description in the drop down messages.
Initially we thought it could be due to those pins were not assigned to any logic internally, so we tried to set a couple of SDI cores as transmitter and receiver taking as reference the design examples available in the IP parameter editor.
In this case, keeping only the pins connected to any internal logic we got the following errors:
These are signals inside the receiver SDI IP core, we don’t know how to fix this problem.
After facing that issue, we tried to generate the “serial loopback” SDI example, selecting as target development kit “Nextera VIDIO 12G-SDI FMC card” and board ”Agilex 5 I-Series SOC Development kit” in Quartus 24.3.1. Taking this design as base we tried to only modifying some pins to match our needs. In this case we got the following error:
Attached you can find the archived project of the example in case it could be of interest.
At the moment we are stuck on this topic and running out of ideas, we tried with Quartus 24.2.0, 4.3.1 and 25.1 with same results. Maybe we are missing something or doing something wrong.
Link Copied
Hi,
I check the attached .qar file.
AV16/AV21 are dedicated pins for XCVR reference clock, those can't be used directly in fabric/IOPLL.
Please check back on your design/schematic of the Arrow board , perhaps try to assign another pin on it.
When I compiling your design, i saw below three pin is fail to justify, comparing to design generate for Agilex 5 premium devkit
After facing that issue, we tried to generate the “serial loopback” SDI example, selecting as target development kit “Nextera VIDIO 12G-SDI FMC card” and board ”Agilex 5 I-Series SOC Development kit” in Quartus 24.3.1. Taking this design as base we tried to only modifying some pins to match our needs. In this case we got the following error:
>> Sorry I am bit confuse on this statement, from the shared .qar , i see the design is Agilex5 .. why not you try to migrate the Agilex5 design generated from the IP catalog to your existing Arrow board ?
>> I try to compile the design via devkit, and i get the compilation pass 100 % without any error
>>
Regards,
Wincent_Altera
Hi,
Thank you very much for your response.
Sorry if my previous explanation lead to confusion. As you suggested, we have been trying to modify the pinning of the generated design to be compatible with our development board.
While we were able to compile the original generated design, when we modify the pins we are getting errors.
Accordngly to the pinning file, the pins we intend to use should be right, aren't they?
Trying to compile we get the following errors in Fitter stage
We are a bit confused here, as we understand the pins are properly assigned.
Attached can be found the generated design with our pinning modifications.
Best regards
Hi,
Thanks for your response.
Even if we are using another devkit, accordingly to the pin function our pinning selection should be ok, right?
What if we intend to develop our own board design? We need to be sure that the pinning chosen would be valid.
In case those pins or others could not be used we need to understand the reason why.
Best regards
