SERDES in Cylone III

[Altera_Forum]

Hi, 

 I am trying to implement a serializer on a Cyclone III EP3C5F256C6. My design is to take 66 LVTTL/LVCMOS inputs and one clock at 133MHz and using a serialization factor of 6, output 11 LVDS outputs with a LVDS clock at 399 MHz and an overall data rate of 798 Mbps/lane. The design is fairly simple and basically uses the ALTLVDS megafunction to implement the serializer. The project compiles successfully, however I have never used a timing analyzer before, and I am having problems generating some test waveforms so that I can verify the functionality of this device before the board is built. I really just need some simple waveforms to quickly verify that my design will function correctly and I have been using the classic timing analyzer with a vector waveform file (.vwf). Any waveforms that I create cause very strange results on the outputs and I am not sure if I just do not know how to use the tool properly, or if there are problems with my design.  I have attached my project, so if anyone of you experts have a few quick seconds, any tips or recommendations to help me get started would be extremely helpful and I would really appreciate it. If not too much effort, I would appreciate it if someone could make any changes to my files and resend back to me.

[Altera_Forum]

I have exactly the same problem! I 'm trying to implement a 48-to-12 ALTLVDS-SERDES circuit for the Cyclone III, that reads data from a RAM memory at CMOS and writes it to a DAC at LVDS. When I use the Vector Waveform Files to simulate my design it makes absolutely no sense to me. Isnt't this SERDERS circuit supposed to function like some kind of multiplexer? pappaloo's post hasn't been answered for about a year. I hope this is not that difficult to figure out! Any help would be appreciated.Thank you