SERDES to PCIe4 in Agilex

[victor4]

I am just beginning a design conceptualization where I will use an Agilex FPGA to receive 16-32 lanes of SERDES CML data which has a similarity to XAUI packets including start/stop, sync, error, and 8B/10B encoding bits.  All incoming lanes operate at 3.125 Gbps.  I have to convert the data to PCIe4x4 because I will be sending it to two Optane P5800X SSDs for storage with a throughput data rate approaching 9GBps.  I need to know if the data can be converted and directed into two PCIe buses in real time.  I've not used the F-tiles before so I do not know how much latency there is with the conversion nor whether the data conversion can be handled in the fabric without having to be touched by the processor. 

[Harris]

Hi Victor,

From your description, FPGA should work as PCIe root port mode, and SSD works as EP mode. PCIe system needs to work with software for enumeration, configuration space registers setting, etc. For your case, it is impossible to send data directly to PCIe. You need to use RAM/FIFO to buffer data from Serdes, then design DMA controller to move data from the RAM/FIFO to PCIe endpoint(SSD). Thanks.

BR/Harris  

[victor4]

Thank you for your reply. 

Due to my project schedule and the longer lead time for the Agilex (which supports PCIe4), I may have to use Stratix parts instead.  However, Stratix only supports PCIe3.  If I have a total data output of almost 9GBps, this will require 3 or 4 PCIe buses to store the data to an SSD drive.  Can the data successfully be divided into 4 PCIe3 buses for storage?  If so, is this done in the DMA controller?

[Harris]

Hi Victor,

Every PCIe bus works independently. In theory, the whole throughput can be divided into 4 parallel parts, but it depends on your design. DMA controller only works for data movement, it don't support this division function. Thanks.

BR/Harris