SFL Production System

[Altera_Forum]

I am using an EPC40 in AS mode with an EPCS16 flash device. 

 Our design is complete and works as expected when programming directly to the AS device. Now for our production environment we are trying to program the AS device in-circuit using the JTAG interface and a 3rd party JTAG programmer.  My initial method was to generate a JIC (works with QuartusII and a ByteBlaster) and generate a JAM file from the JIC as specified in AN350. For some reason the 3rd party JTAG software did not like it.  My second method and the one that I want to get working now is to use an SFL image running in the FPGA and then program the AS device through the JTAG as per AN350. I have generated a basic QuartusII project for the EP3C40 and instantiated the SFL which builds ok. Using a ByteBlaster for initial test purposes I program the FPGA with the SFL image using the SOF file. Then I program the final design image to the FPGA also using its SOF file but for some reason it does not get programmed in to the AS device. I know this because I have also monitored DCLK signal during the final configuration phase. I also tested the same principal using the default SFL SOF image located in the QuartusII installation path.  This seems quite fundamental and it looks like others have got this working unless they have only used JIC files which works for me also.  Please help.

[Altera_Forum]

After you upload an image with an SFL to the FPGA, you should do an "automatic detect" in Quartus programmer. You should then see a new component in the JTAG chain which is the EPCS flash. You can then use the Quartus programmer to upload your design in the flash.

[Altera_Forum]

--- Quote Start ---  You should then see a new component in the JTAG chain which is the EPCS flash. You can then use the Quartus programmer to upload your design in the flash.  --- Quote End ---    Yes the autodetect works and I can see the EP3C40 with an EPCS16 tagged off it. If I try and assign an image file to the EPCS16 entry it will only let me add a JIC file, I want to add the SOF or JAM. I am probably doing this wrong because it seems odd that it only limits me to a JIC as this file type already has the SFL integrated which defeats the object of pre-loading the SFL in the FPGA.

[Altera_Forum]

The Quartus programmer needs a .jic file to program an EPCS through the SFL, and doesn't automatically do the convertion from a .sof. I don't really know the reason for this limitation, as it adds some extra steps. 

You need to convert your .sof into a .jic, and then use the programmer to flash it into the EPCS chip. Have a look at an370 (http://www.altera.com/literature/an/an370.pdf) for more details.

[Altera_Forum]

--- Quote Start ---  You need to convert your .sof into a .jic, and then use the programmer to flash it into the EPCS chip. Have a look at an370 (http://www.altera.com/literature/an/an370.pdf) for more details.  --- Quote End ---    Thanks Daixiwen I think this concludes that I cannot achieve what I was hoping as I am using a 3rd party JTAG system on our production line and required JAM files - hoping to put the SFL in the FPGA followed by the final JAM image in to the AS device.  I think I will have to go back to the JTAG supplier and work out why it didn't work with my JAM file created from the JIC i.e. with the SFL integrated. :confused:

[Altera_Forum]

I've never done it with a third party JTAG tool, but according to the application note it should be possible, so I agree that you should ask your JTAG supplier. 

Just be sure to create and use two JAM files, one that flashes the SFL image into the FPGA and one that uses it to put the design into the flash memory.

[Altera_Forum]

I am currently talking to our JTAG provider concerning the JAM file created from the JIC, looks promising at this stage. 

   --- Quote Start ---  Just be sure to create and use two JAM files, one that flashes the SFL image into the FPGA and one that uses it to put the design into the flash memory.  --- Quote End ---    I tried this out using a standard ByteBlaster but what happens is that after the SFL is loaded in the FPGA when you program the final image it is just overwriting the SFL in the FPGA's SRAM i.e. not going through the SFL. Therefore as you mentioned earlier I am fairly sure you have to use the auto detect and attach a JIC file to use the pre-loaded SFL.

[Altera_Forum]

Did you follow the procedure in the application note to create the second .jic and .jam files? You must be sure that the generated jtag indirect file goes through the SFL. From what you are describing it seems that the .jam file that you use is wrong and just configures the FPGA, just like the first one (the one that places the SFL in the FPGA).

[Altera_Forum]

Yes I followed the application note and it works fine when using the JIC/JAM files with the Altera tools. 

 At the moment I can not get the JAM with integrated SFL to work with our production system and other JTAG tools.