SOPC Internal Error: std_logic ports/signals must be width 1

Altera_Forum · ‎07-13-2009

I've upgraded from v8.1 to v9.0sp2. Some custom components I've been using are now throwing the following error when I try to generate my SOPC system.

Error: <componet name>: Internal error: std_logic ports/signals must be width 1.

I found a similar thread (http://www.alteraforum.com/forum/showthread.php?t=4347) but it doesn't provide any solutions.

My components are all written in VHDL. I went through the process of removing all existing .tcl files and recreating them in v9.0sp2. I tried replacing all std_logic statements with std_logic_vector(0 downto 0), but the same error still occurs.

What does this error mean? Does anyone know how to fix the error? Does anyone know a workaround?

Thanks

Altera_Forum · ‎07-13-2009

do you have any integers in the ports list?

Altera_Forum · ‎07-13-2009

No, there are no integers, just std_logic and std_logic_vector.

Altera_Forum · ‎07-22-2009

There is a bug in v9.0. SOPC builder no longer understands any custom components with a top-level declaration containing any data type besides std_logic and std_logic vector. For instance, if you have an unsigned, signed, or integer port, then attempting to generate your SOPC project generates the above error.

The workaround is to refactor your component to use std_logic and std_logic_vector in the declaration. So, if you had an avalon slave interface with a signal named avs_s1_address you need to change:

avs_s1_address : in unsigned(2 downto 0);

to

avs_s1_address : in std_logic_vector(2 downto 0);

Later in your code you can declare a signal addr like this

signal addr : unsigned(2 downto 0);

and then assign it to the port signal like this

addr <= unsigned(avs_s1_address);

Now you can use the unsigned type addr in your code and SOPC is happy because the port is a std_logic_vector.

Altera_Forum · ‎11-20-2009

great this was working for me!!

passing from std_ulogic to std_logic solved it.

Thanks a lot:)