SOPC ModelSim Simulation

[Altera_Forum]

I want to simulate my SOPC system(without NIOS) with ModelSim Altera but I ran into this error: 

  --- Quote Start ---   ALTERA version supports only a single HDL# ** Error: (vsim-3039) D:/DSO/Projekt/Main/dso_sopc.vhd(67): Instantiation of 'SPISlaveToAvalonMasterBridge' failed.# Region: /testbench/dut/b2v_inst/the_spi_slave_to_avalon_mm_master_bridge_0# Loading work.dso_sopc_reset_clk_ad_domain_synch_module(europa)# Error loading design  --- Quote End ---   I've selected SOPC Builder to generate VHDL files, but there are still some Verilog files generated. For my files I use VHDL. ModelSim doesn't support mixed projects? What can I do?

[Altera_Forum]

ModelSim does support mix VHDL and Verilog files. Looks like your error is result of a missing instance. check if you have all files compiled.

[Altera_Forum]

--- Quote Start ---  ModelSim does support mix VHDL and Verilog files. Looks like your error is result of a missing instance. check if you have all files compiled.  --- Quote End ---   ModelSim-Altera Edition as mentioned in the original post does not support mixed language.

[Altera_Forum]

So, does that mean, that there isn't any way to simulate my SOPC design, if I wrote my own components in VHDL and connect them to standard Altera components which were written in Verilog? 

 This would be stupid, wouldn't it?

[Altera_Forum]

The Altera components can be generated in either VHDL or Verilog. Select the language to use in the megawizard.

[Altera_Forum]

Hello Daixiwen, 

 thanks for your answer!  I just built a new design with SOPC builder using my own VHDL components and one Altera component (Altera Avalon ST-Sink BFM).  In the SOPC System Generation Tab there is shown "System module logic will be created in VHDL".  But, when running ModelSim there is the following error: # ALTERA version supports only a single HDL# ** Error: (vsim-3039) C:/Test/sopc_system.vhd(543): Instantiation of 'st_sink_bfm_0' failed.# Region: /test_bench/dut  When opening the project directory there is also a "st_sink_bfm_0.v" file. It's Verilog. Where can I choose to generate this component in VHDL?  I'm sorry, I didn't get it yet..........  Thanks for your assistance!  Best Regards!

[Altera_Forum]

After verification it seems that the BFMs used by Altera in the Avalon Verification IP suite only exist in Verilog, contrary to all their synthesizable IP. 

I'm afraid your only solutions are to use another simulator that supports mixed language, or write your own BFMs in VHDL in your test bench.

[Altera_Forum]

Ok, thanks for your verification! I'll don't use the Altera BFMs in future. Probably I'll write my own, as you suggested... 

 Thanks a lot again!