SPI Slave Timing Constraints

[SK_VA]

Hi,

I have an SPI slave implemented in FPGA with input SCLK clock ranging between 10-20MHz.

I have added two flop synchronizer for all SPI input signals CS,SCLK,MOSI before using them in the Slave logic.The two flop synchroniser operates at a very high frequency of 100MHz.

I saw in one of the altera forum posts that SPI slave where all the inputs are synchronized with a double register-chain doesn't need to be constrained.

But if I set them as false path how does the fitter know the timing relation between SCLK,MISO and MOSI. Do we need to consider SPI as a source synchronous interface?

How to estimate the setup and clock to output timing of this interface?

[KhaiChein_Y_Intel]

Hi,

You cannot set false path if you want to know the timing relationship between the signals. To constrain a source synchronous interface, you may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an433.pdf

Thanks

Best regards,

KhaiY

[SK_VA]

Hi,

Thanks.

I am using a two flop synchronizer that runs at a higher frequency  for all the SPI slave inputs including clock. Do I need to constrain with a virtual clock of higher frequency or wrt spi slave clock input as source synchronous.

[KhaiChein_Y_Intel]

Hi,

You have to constrain the virtual clock that connect to the clock pin of the source data signal.

Thanks

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi,

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

Best regards,

KhaiY