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Altera_Forum
Honored Contributor I
1,024 Views

SRAM DS2064 into a CPLD

Is it a good idea to implement a SRAM DS2064 (8 bit x 8k) into a CPLD? 

 

After a lot of internet research, I was unable to find a VDHL code for it. 

 

I just attached the DS2064 for reference. 

 

Thanks!
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Altera_Forum
Honored Contributor I
121 Views

Why would you want to do that? 

 

FPGAs (most all) have internal block RAMs that could implement that storage in about 4-8 BRAMs. CPLDs usually have no internal block RAM, so you'd have to implement as logic.
Altera_Forum
Honored Contributor I
121 Views

If "CPLD" is used as a generic term including FPGAs like MAX10, you can implement a similar RAM in it. Consider that due to the synchronous architecture of FPGA block RAM you can't exactly model the behavior of an asynchronous SRAM. Depends on the application if this matters.

Altera_Forum
Honored Contributor I
121 Views

Ok, thanks for the info. 

 

I always used CPLD only for logic, not for memory.
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