Why would you want to do that?FPGAs (most all) have internal block RAMs that could implement that storage in about 4-8 BRAMs. CPLDs usually have no internal block RAM, so you'd have to implement as logic.
If "CPLD" is used as a generic term including FPGAs like MAX10, you can implement a similar RAM in it. Consider that due to the synchronous architecture of FPGA block RAM you can't exactly model the behavior of an asynchronous SRAM. Depends on the application if this matters.