SRAM SOPC cy7c1380, phase clk

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

SRAM SOPC cy7c1380, phase clk

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Hello,

According with the documentation of the module available with SOPC Builder for the SRAM CY7c1380c, I have to set a phase shift to the clock of the SRAM.

This phase shift depends of the Tpd(PCB), Tc0(SRAM) and Tsu(FPGA).

If I check the datasheet of the memory I can see that is specified a different Tco, depending of the frequency (please, look attached file).

I do not know what is the Tpd of my PCB, it is not a Development Kit, is a board designed by a friend.

If I am working at 24MHz and with a Cyclone 2 speed grade 8, how must I set this value?.

I have already read the documentation but is not clear for me. They talk of differents Tco.

../90sp1/quartus/sopc_builder/documents/ssram_interface...

Sugestions?

Thank you.

DABG.

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